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Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.

Continuous enhancement of the performance of energy harvesters in recent years has broadened their arenas of applications. On the other hand, ample availability of IoT devices has made radio frequency (RF) a viable source of energy harvesting. Integration of a maximum power point tracking (MPPT) controller in RF energy harvester is a necessity that ensures maximum available power transfer with variable input power conditions. In this paper, FPGA implementation of a machine learning (ML) model for maximum power point tracking in RF energy harvesters is presented. A supervised learning-based ML model-feedforward neural network (FNN) has been designed which is capable of tracking maximum power point with optimal accuracy. The model was designed using stochastic gradient descent (SGD) optimizer and mean square error (MSE) loss function. Simulation results of the VHDL translated model demonstrated a good agreement between the expected and the obtained values. The proposed ML based MPPT controller was implemented in Artix-7 Field Programmable Gate Array (FPGA).

D, T, SR, and JK fuzzy flip-flops are proposed and their characteristics are graphically shown in four—max-min, algebraic, bounded, drastic—logical operation systems. Some properties of there logical forms are analytically shown. The circuits of the proposed flip-flops are designed and simulated on VHDL circuit simulator. The result of synthesis shows that the areas of D, T, SR fuzzy flip-flops are nearly 0, 2/3 1/2 of that of JK fuzzy flip-flop and the delay times of D, T, SR fuzzy flip-flops are nearly 0, 2/3, 2/3 of that of JK type, respectively.

Triple DES is the most widely use symmetric cryptographic algorithm. It has many applications in communication and financial area. Operations in triple DES algorithm, such as: permutation, circular shifts, and S-box transformations are time consuming and can not be efficiently processed by traditional CPUs. In this essay, we have explored the tradeoffs in designing a triple DES reconfigurable processor. The optimization techniques we have explored include: parallel processing, loop unfolding, and pipelining. We have evaluated our design on the Xilinx XC2V1000 FPGA platforms and get a throughput of 6973.2Mb/s for triple DES operation.

Introduces some refer conceptions of the PCI bus and issues the finite machine design in PCI bus interface controller. Implements a PCI bus controller in programmable device FPGA by using VHDL language. The result of test indicates that this design accords with sequence request of PCI criterion and get a good effect.

Detecting and tracking interesting moving targets are crucial steps in intelligent video surveillance. We proposed a combination algorithm of Frame Difference and Particle Filter accelerated by FPGA parallelism. Parallel pre-processing and post-processing are added to Frame Difference to increase the anti-interference of detection. The improved Particle Filter hardware architecture can judge the tracking and lost status of moving targets by comparing the threshold of particle weight and the number of degenerated particles. Multi-target detection and tracking are implemented by reusing detection and tracking modules. Experimental results show the proposed hardware architecture shows great detection and tracking accuracy and real-time performance.

Using the advanced encryption algorithm AES ^[1][2], an encryption and decryption IP core is designed for embedded processors. Using the FPGA on-chip storage module and the reconfigurable S box, the key and the original data are managed with a dedicated storage method, to be locked in the kernel. In order to make the IP core able to be flexibly used in the Nios II embedded system, the corresponding interface and its address mappings are designed in accordance with the Avalon bus interface specifications. The IP core can thus be easily customized in the Nios system. The Nios II processor, customized encryption and decryption components, network controller, memory and other corresponding peripheral equipment are composed to a hardware platform by using SOPC technology. For the purpose of automation control, corresponding software is written to make it a real-time network encryption and decryption system.

This paper describes a wireless spectral sensing network (WSSN) applied in mushroom workshops, which is capable of measuring the near infrared spectrum and the environmental parameters. With the sensing ability of chemical compositions, the WSSN can be used to provide scientific guidance for mushroom cultivation. As the network's core unit, the spectral sensing node uses, uniquely, a new monolithically integrated multichannel spectral sensor (MCSS). A multichannel integrated narrow-band filter array, an uncooled InGaAs detector array and a readout circuit are integrated into the MCSS. Benefiting from the monolithic design of MCSS, the size and complexity of the spectral sensing node is reduced. A field programmable gate array (FPGA) is used to control the whole measurement process and wireless communication. The discussion in this paper focuses on the design and performance of the spectral sensing node.

Improving network transmission efficiency is an important issue in 10 Gigabit Ethernet (10GigE) transmission. FPGA functions by receiving, sorting, combining and repacking required UDP protocol frames, before sending them to the downstream receiver. This design has high efficiency and low delay through FPGA hardcore programming. The start, stop and necessary parameters for the frame reconstruction are controlled and configured by the upper computer software, providing easy modification and good adaptation. The design can effectively improve the utilization of 10GigE transmission link, optimize the network environment, and enhance the processing efficiency of downstream receiving device.

Traditional FPGA placement algorithms based on simulated annealing is time-consuming and thus we have proposed a parallel FPGA timing-driven placement algorithm using OpenMP + STM programming method. In this paper, we distribute swaps to multithreads by OpenMP and protect the shared memory using software transactional memory. An improved timing optimization algorithm is also added in the transaction. Experimental results on MCNC benchmarks demonstrate that our algorithm achieves a speedup of 1.6x and scales well with the increasing of threads. It also reduces the critical path delay by an average of 4.2%.

Software testing plays an important role in software quality and reliability assurance, especially the ergodic and effectiveness of FPGA and other embedded software testing need further research. Aiming at tackling the coverage and effectiveness of FPGA embedded software testing, major problems in the process of FPGA software testing are analyzed, testable design and verification program based on digital simulation are brought forward. Top-Down design for testability, combined with system-level simulation and digital quantization is introduced to produce complete input and output test vectors based on system-level model or algorithm. The test vector and hardware description language input and output modules are compared to verify the design correction of FPGA software code module function wholly. A FPGA software testing process is established at all stages of the software development, combined with the actual situation of testing and verification.

IRFPA has become the leading chip in Infrared domain. Infrared trackers use different image size, such as 320×240 and 256×256. In order to simulate these trackers, a method is proposed which uses detector’s optional window format. It uses low noise technology to design the peripheral circuit and precision voltage reference to realize the bias voltage. All of the detector’s digital signals are insulated by optocouplers. FPGA is used to realize most of the functions, such as interface control, windowing mode, analog to digital convert, video display, RS422 interface and algorithms of non-uniform correction, automatically blind pixel elimination, etc. It can be used in many fields, such as proving the algorithm of recognition and tracking. The results show that the imaging system has the advantages of good image quality, good environmental adaptability, good expansibility and high reliability.

Visible Light Communication (VLC) technology has aroused great attention these days as Light Emitting Diode (LED) is becoming the dominant source for artificial lighting. Previous research on VLC mainly focuses on the high speed transmission, which not only brings about extraordinary implementation complexity but also severely impairs the communication distance. This paper resolves low speed application scenarios, and proposes a simple implementation for VLC with long communication distance. A demo system without extra complex devices is set up as well. Test result demonstrates that the proposed VLC system can realize reliable optical wireless communication between two Personal Computers (PCs) at the distance of several meters, which contributes to the practical development of VLC technology.

Most Advanced Driver Assistance Systems (ADAS) make use of the line model to represent the lane markings, which is simple and convenient, but not well modeled the curve lane. This paper proposed a Field Programmable Gate Array (FPGA) based method to detect the curve lane markings for ADAS. The main idea is that extracting the line model of the lane markings independently in three parts segmented by actual distance in vehicle coordinate to get the feature points of lane markings for fitting the hypothetical curve model. We divided the processing modules into two computing structures: PL and PS, and the reusable IP core of Hough Transform (HT) in FPGA was made use of to solve the poor real-time performance. Experiments illustrate the feasibility of the introduced method and higher performance than the method used line model.

When micro grid is in the state of off grid operation, the voltage stability is maintained by energy storage inverter. Due to the small capacity of micro grid, energy storage level and load changes can easily cause the deterioration of the waveform quality of the system voltage. In order to solve this problem, a new voltage inverse control scheme of energy storage inverter is proposed based on neural network. For the purpose of real-time performance, the design of the neural network special arithmetic unit is implemented using FPGA, and comparison of the implementation schemes for excitation function is carried out. Simulation results show that the proposed scheme is feasible and effective.

Enhancing the line spetrum of ship-radiated noise by Adaptive Line-spectrum Enhancement is good to detect and extract line spectra. An improved adaptive line enhancement method of line-spectrum detection is used. To solve the problem that adaptive line enhancer implemented by FPGA through bttom layer HDL coding has a poor development efficiency, a model of improved adaptive line enhancer is established by DSP Builder and files which can be used by FPGA are generated automatically. Then the improved adaptive line enhancer is simulated by the simulation model, and the feasibility of the model is validated. It is easy and simple to design adaptive line enhancer by using this method.

DSP (XC2267) is the main control chip which does the increment PI algorithms and realizes the voltage and current double closed-loop control. Three-phase thyristor rectifier method based on the phase self-adjusting of FPGA is proposed. A method for sweptfrequency start circuit is designed to implement the transition between the high-power and low-power. The invert system uses the compound control of improved PWM and frequency phase lock to improve the control accuracy and efficiency. Lastly, by using bench, the circuit is tested and the feasibility and effectiveness of the whole system are verified.

This paper discusses the modeling, simulation and synthesis of automatic digital modulation identification algorithm for Software Defined Radio on a dynamically and partially reconfigurable heterogeneous platform. Implementation results highlight the benefit of considering a FPGA platform instead of a multi-DSP platform since the FPGA supports efficiently intensive computation components, which reduces the DSP load. The proposed method has been modeled, simulated and synthesized for the target device of Xilinx Virtex-E v3200efg1156 FPGA. The obtained results show that the chip utilization is less than 32% and the propagation delay is 70.396 ns for the selected target device.

This paper presents a complete artificial vision system development and implementation for a mobile robot recognition and obstacles detection, which integrates a statistical segmentation method with frequency filtering in order to achieve luminosity independence, exploiting the advantages of known image processing techniques by mixing them into a robotic application. The system proposed determines the mobile robot's position and orientation, using a color segmentation approach based on the Mahalanobis Distance, and the position and size of obstacles in the robot's environment using a parallel scheme based on both Sobel edge detector and Otsu's threshold. The Mahalanobis distance calculus was implemented using a real-time PPGA architecture, in order to detect the robot's position. Tests in the real robot's environment are presented obtaining results that are independent from the background characteristics and strongly robust on the luminosity variability.

The complexity of signals and of algorithmic methods in medical signal processing tasks imposes considerable requirements on the computing hardware. The conflicting demands for computing power and portability can currently be satisfied only by massively parallel operation. In this contribution we present the CESAR architecture of a parallel processor array utilising the underlying Cellular Nonlinear Network principle. The array is embedded into a hardware-software system forming a highly configurable signal processing platform usable both in algorithm development and in real-world applications.