Narrow Results

We have fabricated, characterized and compared the performance of lateral enhancement-mode GaN MOSFETs on as-grown and RIE-etched surfaces with 900 and 1000°C gate oxide annealing temperatures. Both subthreshold swing and field effect mobility show 1000°C is the optimal annealing temperature for the PECVD gate oxide in our MOSFET process.

The performance of organic thin film transistors (OTFTs) strongly depends on the surface states of the gate insulator. Top-contact (TC) OTFTs with modified gate insulator were demonstrated in this paper. The modified gate insulator layers consisted of SiO₂ as the gate insulator and OTS (octadecyltrichlorosilane) or PMMA (Poly (methyl methacylate)) as the modified layer. The devices with the modified layer had field-effect mobility larger than 10^-3cm²/Vs, which was twice that of the untreated OTFT. The on/off current ratio was increased one order of magnitude and reached more than 10⁴. The leakage current was decreased from 10^-9 A to 10^-10 A. The results demonstrate that using modified gate insulators can obviously improve the performance of the OTFTs.

In order to investigate the feasibility of gating organic field-effect transistors (OFETs) using a photosensitive photoresist material, pentacene-based OFETs were fabricated on indium tin oxide (ITO) glass. The gate dielectric was found to be easily patterned by spin coating and UV exposure, and has an excellent surface roughness of 0.22 nm and good insulating properties, resulting in a low leakage current (49 nA at 2 MV/cm) at a dielectric thickness of 290 nm. The OFET with photopatterned gate dielectric exhibited good electric characteristics, including a high field-effect mobility of 0.15 cm²/Vs, a threshold voltage of -9.9 V, and on/off current ratio of ~10⁴. The high matching of surface free energy between the gate dielectric and pentacene is proved to be contributed to the good performance of the device.

We have fabricated, characterized and compared the performance of lateral enhancement-mode GaN MOSFETs on as-grown and RIE-etched surfaces with 900 and 1000°C gate oxide annealing temperatures. Both subthreshold swing and field effect mobility show 1000°C is the optimal annealing temperature for the PECVD gate oxide in our MOSFET process.