Narrow Results

We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal directions was investigated for different channel geometries. The biasing condition which enables the simultaneous activation of all channels and gives rise to volume inversion is discussed.

The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be exploited for bio-applications. In this manuscript TCAD results are presented on the analog and digital performance of the Screen-Grid Field Effect Transistor. The results are compared to the operation of an SOI-MOSFET and a finFET.

We have fabricated and investigated several types of GaN MOSFETs with normally-off operation. The recessed-gate GaN MOSFET is preferred for normally-off operation, because the threshold voltage (V_th) of the device can be easily controlled, but it suffers from relatively modest current drivability which must be improved by adopting appropriate device structure and/or process. Enhanced performances have been achieved in this work by combining the recessed-gate technology with additional processes, such as: the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, the post-deposition annealing of gate oxide to decrease the gate leakage current, the re-growth of n+ GaN layer for source/drain to improve the access resistance and V_th uniformity, the stress control technology to achieve extremely high 2-D electron-gas density (2DEG) on source/drain and decrease the series resistance, and the use of the p-GaN back-barrier to decrease the buffer leakage current. The GaN-based FinFET with very narrow fin was also investigated as a possible candidate for high performance normally-off GaN MOSFETs.

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

The thermal performance of two-dimensional (2D) field-effect transistors (FET) is investigated frequently by solving the Fourier heat diffusion law and the Boltzmann transport equation (BTE). With the introduction of the new generation of 3D FETs in which their thickness is less than the phonon mean-free-path it is necessary to carefully simulate the thermal performance of such devices. This paper numerically integrates the BTE in common 2D transistors including planar single layer and Silicon-On-Insulator (SOI) transistor, and the new generation of 3D transistors including FinFET and Tri-Gate devices. In order to decrease the directional dependency of results in 3D simulations; the Legendre equal-weight (P_N-EW) quadrature set has been employed. It is found that if similar switching time is assumed for 3D and 2D FETs while the new generation of 3D FETs has less net energy consumption, they have higher hot-spot temperature. The results show continuous heat flux distribution normal to the silicon/oxide interface while the temperature jump is seen at the interface in double layer transistors.

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I${}_{\mathrm{\text{off}}}$) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I${}_{\mathrm{\text{sat}}}$) of the PMOS. In order to sustain I${}_{\mathrm{\text{off}}}$, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I${}_{\mathrm{\text{off}}}$ = 1 nA/um, the best performance I${}_{\mathrm{\text{sat}}}$ = 856 uA/um is at L = 34 nm for 14 nm FinFET and I${}_{\mathrm{\text{sat}}}$ = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32nm technology node at 25${}^{\circ }$C and 110${}^{\circ }$C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25${}^{\circ }$C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% in SG mode and in LP mode a maximum saving of 95.10% at 25${}^{\circ }$C is achieved. Similarly, DGNPT saves 99.34% in SG mode and in LP mode it saves 99.90% leakage power at 25${}^{\circ }$C with respect to conventional gates. The proposed techniques are also applied on different benchmark circuits and the results are validated. As an application of the proposed techniques, NAND gate is modified accordingly and it is used in 1-bit and 2-bit full-adder circuits.

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–$3.82\times$ higher compared to different existing techniques in FinFET SG mode and is 1.42–$3.29\times$ higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to $7.44\times$ higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

This paper presents an optimal design of a high-performance multi-output second-generation current conveyor (MO-CCII) based on 20nm Fin-Shaped Field Effect Transistor (FinFETs). Proposed MO-CCII has very low port X impedance and very high port Y impedance. The performance of the CCII has been thoroughly investigated in terms of DC, AC and transient characteristics of terminal voltages and branch currents and frequency response of port impedances. CCII shows the excellent high-frequency response of voltage as well as current transfer gains. The 3dB BW of voltage and current transfer gains are 11.2GHz and 11GHz, respectively. CCII provides excellent performance over its CMOS counterpart. Also, a resistor-less multi-function bi-quadratic filter is proposed. The filter depends on two CCIIs, a capacitor and does not require any resistors. It has three inputs and one output and realizes low-pass, high-pass and band-pass filters from a similar setup. FinFETs in the linear region are utilized as variable resistor to control filter properties. Nevertheless, the proposed filter has two floating capacitors which can be effortlessly realized in these days’ integrated circuit advancements. Also, a balanced modulator is proposed utilizing the proposed FinFET-based CCII and FinFET transistors only. Balanced modulator’s frequency of operation obtained is in GHz range.

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with $\pm 10$% deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations.

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation $\sigma /\mu (\%)$ for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation $\sigma /\mu (\%)$ for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (g_m) to drain conductance (g_d). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material.

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

With transistors reaching nanometer dimensions, dissipated energy has become of great importance in recent years. A practical approach to reducing energy consumption is to use logic-in-memory (LIM) structures based on magnetic tunnel junction (MTJ) devices combined with approximate computing. In this paper, we propose energy-efficient MTJ/FinFET-based approximate 5:2 compressors for error-resilient in-memory computing, providing an accuracy close to the exact design (1.54% error rate) while reducing the energy consumption by more than 50%. The innovative Boolean equations and the structure of the proposed approximate circuits based on spin-Hall effect assisted MTJs lead to a significantly more effective compromise between energy and accuracy than the previous exact and approximate counterparts. The simulation results provided using HSPICE with 7nm FinFETs and SHE-assisted MTJ models demonstrate the superior hardware parameters of the proposed designs. Furthermore, the MATLAB simulations show an average peak signal-to-noise ratio (PSNR) of more than 43 and an average structural similarity index metric (SSIM) of more than 0.99 across image multiplication, sharpening, and smoothing operations.

In this work we simulate the dependence of the amplitude of the random telegraph noise (RTN) on the gate overdrive (overload) for SOI FinFET with a cross section of rectangular and trapezoidal channels. It is shown that in the sub-threshold area when a single interface charge is detected in the middle of the RTL interface, the amplitude of the RTN is much higher for the cross section of the trapezoidal channel. In contrast, the amplitude of RTN is higher for a rectangle than for a cross section of a trapezoidal channel when the charge of an interface is detected at the upper channel interface. We also consider the dependence of the RTN amplitude on the position along the transistor channel, the charge of a single interface, which is detected at the upper interface, and on the side channel interface.