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This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

Floating-body-induced transient mechanism in advanced FinFETs was investigated for unified and multi-bit memory capability. Nonvolatile memory operation was achieved by modifying the SOI buried insulator (BOX) such as the SiO₂-Si₃N₄-SiO₂ (ONO) BOX can accumulate permanent charges. Charges are injected/removed in the Si₃N₄ layer by back-gate or drain bias and sensed remotely, by gate coupling, through the modulation of the drain current flowing at the front interface. On the other hand, the isolated silicon body of the transistor can store volatile charges, generated by impact ionization and able to modulate the drain current flowing at the back interface. Our experimental results successfully demonstrate that these two different memory modes can be advantageously combined for multi-bit volatile memory operation. The volatile memory behavior strongly depends on the distribution of the nonvolatile charges stored in the nitride buried layer. Our measurements manifest that the nonvolatile charges located near the drain terminal have larger influence on the volatile memory operation than the charges located at the opposite terminal. Also, we reveal that the bias conditions and device geometry are important factors for the two memory modes.

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves $66\%$ reduction on the average number of activated comparators compared to a conventional flash ADC.

A functional polyimide (CF3 PI) was used as the active layer in our present work for electrical resistive memory device applications. Current–voltage ($I$–$V$) characteristics analysis on the polyimide memory devices indicates that the polyimide possesses a nonvolatile rewritable flash characteristic with an ON/OFF current ratio of about 10⁴ at the threshold voltage of around $-1.2$V and 3.8V. In addition, the device using the CF3 PI as the active layer reveals excellent long-term operation stability with the endurance of reading cycles up to 10⁸ under a voltage pulse and retention times for at least 10⁶s under constant voltage stress (1V). The conduction mechanisms are elucidated on the basis of the thermionic emission theory and filament conduction.

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.