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In-Memory Computing (IMC) is an emerging paradigm that aims to shift computational workload away from CPUs. The bit-serial IMC architecture suffers from larger latency when performing logic and arithmetic operations. In this paper, a general-purpose, energy-efficient Bit Parallel IMC Architecture (BP-IMCA) based on Area-Optimized (AO-8T) static random access memory (SRAM) bit-cell is proposed to perform In-Memory Boolean Logic Computation (IMBC) and Near-Memory Arithmetic (NMA) operations with variable bit-width from 1- to 8-bit. The decoupled read/write paths of the employed AO-8T SRAM bit-cell eliminate compute disturbance during IMBC and NMA operations. A self-terminating read word line decoding scheme is proposed to disconnect the RBL discharging path from GND, which decreases the energy consumption of the proposed IMC architecture by 27.71% at 1V for IMBC operations. In addition to this, a $V_{\mathrm{\text{REF}}}$-based Low-offset Symmetric Differential Sense Amplifier (LSDSA) is proposed to achieve fast and reliable sensing for both normal read and IMBC operations in the proposed IMC architecture. Further, a 4Kb SRAM array is implemented in 65-nm technology to analyze the IMC architecture at a supply voltage of 1V. The operating frequency of 1,355MHz and average energy consumption of 7.04fJ/bit is achieved during logic (IMBC) operations. The 8-bit addition and 8-bit multiplication operations achieve an energy efficiency of 11.1 TOPS/W and 2.28 TOPS/W, respectively, at 1V and 970MHz. Cumulatively, the proposed architecture achieves the lowest figure of merit compared to the state-of-the-art IMC architectures.

Many researchers have focused on molecular electronics, and this field can progress faster by applying semiconductors to molecular modeling. In this work, two middle rings of a bipyridine–biborinine molecular diode are rotated from 25^∘ to 90^∘ such that the current along the molecule is reduced. The current is minimum and almost zero at 90^∘, while it is maximum at 25^∘. Accordingly, considering these two angles, the molecule can act as a switching device when the two middle rings are rotated. The bipyridine–biborinine molecular diode is modeled considering the effect of rotation by including two resistors in the model. Two parallel diodes are used in this modeling for pyridine and borinine rings. The ideality factors of these diodes are varied based on the electronegativity of pyridine and borinine rings. This model is then applied to consider different molecular logic gates such as NAND, NOR, NOT, OR and AND gates, as well as molecular logic circuits (half adder and full adder), using the unique capabilities of the LTspice software.

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs.

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool.

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation $\sigma /\mu (\%)$ for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation $\sigma /\mu (\%)$ for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

A complete analytical model of all optical half adder and full adder is proposed based on phase encoding. This architecture consists of numbers of optical coherent mixers and mirrors. Optical switches are used only in the encoding of inputs, but no such switches are used in the processing part. So real time operation based on this proposed encoding may be achieved. The output of the system always carries the same intensity and therefore it is suitable for using in a combinational and sequential logic system.

This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony with the trend shown in transistor adders.

In the last 50 years, the feature size of the fabrication process for integrated circuits has continuously shrunk, corroborating Moore's Law that the feature size will be halved every 18 months. Recently, however, the problems caused by highly integrated CMOS devices such as large leakage current, high temperature when operating and high energy consumption became a huge barrier impeding the development of integrated circuits. In 1998, CNFET was proposed, and its good electrical characteristics attracted a lot of attention. CNFET is the best potential device to replace traditional CMOS devices. In this paper, a CNFET based full adder with mirror structure was thus proposed, and a comparison between CNFET full adder and conventional CMOS full adder was made.