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During last decades, Cellular Automata (CAs) as bio-inspired parallel computational tools have been proven rather efficient and robust on modeling and simulating many different physical processes and systems and solving scientific problems, in which global behavior arises from the collective effect of simple components that interact locally. Among others of most renowned and well established CA applications, crowd evacuation and pedestrian dynamics are considered ones of the most timely and lively topics. Numerous models and computational paradigms of CAs either as standalone models or coupled with other theoretical and practical modeling approaches have been introduced in literature. All these crowd models are taking advantage of the fact that CA show evidence of a macroscopic nature with microscopic extensions, i.e. they provide adequate details in the description of human behavior and interaction, whilst they retain the computational cost at low levels. In this aspect, several CA models for crowd evacuation focusing on different modeling principles, like potential fields techniques, obstacle avoidance, follow the leader principles, grouping and queuing theory, long memory effects, etc. are presented in this paper. Moreover, having in mind the inherent parallelism of CA and their straightforward implementation in hardware, some anticipative crowd management systems based on CAs are also shown when operating on medium density crowd evacuation for indoor and outdoor environments. Real world cases and different environments were examined proving the efficiency of the proposed CA based anticipative systems. The proposed hardware implementation of the CAs-based crowd simulation models is advantageous in terms of low-cost, high-speed, compactness and portability features. Finally, robot guided evacuation with the help of CAs is also presented. The proposed framework relies on the well established CAs simulation models, while it employs a real-world evacuation implementation assisted by a mobile robotic guide, which in turn guides people towards a less congestive exit at a time.

Fast and robust classification of feature vectors is a crucial task in a number of real-time systems. A cellular neural/nonlinear network universal machine (CNN-UM) can be very efficient as a feature detector. The next step is to post-process the results for object recognition. This paper shows how a robust classification scheme based on adaptive resonance theory (ART) can be mapped to the CNN-UM. Moreover, this mapping is general enough to include different types of feed-forward neural networks. The designed analogic CNN algorithm is capable of classifying the extracted feature vectors keeping the advantages of the ART networks, such as robust, plastic and fault-tolerant behaviors. An analogic algorithm is presented for unsupervised classification with tunable sensitivity and automatic new class creation. The algorithm is extended for supervised classification. The presented binary feature vector classification is implemented on the existing standard CNN-UM chips for fast classification. The experimental evaluation shows promising performance after 100% accuracy on the training set.

Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

Memristor, as a nonlinear element, provides many advantages thanks to its superior properties to design different chaotic circuits. Thus, a novel four-dimensional double-scroll chaotic system with line equilibria as well as two unstable equilibria based on the flux-memristor model is proposed in this paper. The effects of initial values and parameters on the dynamic characteristics of the system are studied in detail by means of phase diagrams, Lyapunov exponent spectrums, bifurcation diagrams, two-parameter bifurcation diagrams and basins of attraction. Besides, a series of complex phenomena in the system, such as sustained chaos, bistability, transient chaos and coexisting attractors are observed, proving that the chaotic system has rich dynamic characteristics. Also, spectral entropy (SE) complexity algorithm and $C_0$ complexity algorithm based on structure complexity are adopted to analyze the complexity of the system. Additionally, PSPICE circuit simulation and Micro-Controller Unit (MCU) hardware experiment are carried out to verify the correctness of theoretical analysis and numerical simulation. Finally, the pulse chaos synchronization is achieved from the perspective of maximum Lyapunov exponent, and numerical simulations demonstrate the occurrence of the proposed system and practicability of the pulse synchronization control.

This paper describes a new visual sensor system for the recognition of touching and overlapping workpieces, designed to meet the requirements of real applications in the factory. The system analyses the grey scale image and comprises two stages: a feature-extraction stage, which is designed mainly in special-purpose hardware, and a model-based analysis stage. The system works with edge-based geometrical primitives and surface features. The model comprises topographical and procedural information in order to control the image-analysis, which is based on the “heuristic-search” technique. The hardware and software design is modular. The system is working well in a wide range of environmental conditions and with different kinds of workpieces. A prototype version is completed and has proved its reliability and performance in several applications in the factory.

This paper, according to the best of our knowledge, provides the very first solution to the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by a significant improvement in the evolution time compared to the time needed for software evolution and efficient use of decision trees in various embedded applications (robotic navigation systems, image processing systems, etc.), where run-time adaptive learning is of particular interest. Several architectures for the hardware evolution of single oblique or nonlinear decision trees and ensembles comprised from oblique or nonlinear decision trees are presented. Proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Results of experiments obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in inference time when compared with the traditional software implementations. In the case of single decision tree evolution, FPGA implementation of H_DTS2 architecture has on average 26 times shorter inference time when compared to the software implementation, whereas FPGA implementation of H_DTE2 architecture has on average 693 times shorter inference time than the software implementation.

In this paper, several hardware architectures for the realization of ensembles of axis-parallel, oblique and nonlinear decision trees (DTs) are presented. Hardware architectures for the implementation of a number of ensemble combination rules are also presented. These architectures are universal and can be used to combine predictions from any type of classifiers, such as decision trees, artificial neural networks (ANNs) and support vector machines (SVMs). Proposed architectures are suitable for the implementation using Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Experiment results obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in the classification time in comparison with the traditional software implementations. Greatest improvement can be achieved using the SP2-P architecture implemented on the FPGA achieving 416.53 times faster classification speed on average, compared with the software implementation. This result has been achieved on the FPGA working at 135.51 MHz on average, which is 33.21 times slower than the operating frequency of the general purpose computer on which the software implementation has been executed.

Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new functional unit called the calculation and anticipation (C&A) unit is presented for the IEEE 754 standard floating-point adder (FPA) that is the most important and frequently used calculation part for both modern CPUs and GPUs. C&A unit parallelize rounding step and readjustment step, which are known as the time-consuming steps for floating-point addition with significand addition. Therefore it reduces FPA critical path delay enormously, and even more decreases a little FPA area occupation. The synthesis results show that the double-precision FPA with C&A unit takes about 17.17% improvement in the critical path delay, while saves about 8.32% area than the conventional one. It takes 5.90% advantage in area and 19.58% improvement in the worst case delay than the double-precision FPA from the Open Core module "fpu_double" (rev 14 2010-02-13) synthesized in the same 0.13-μm CMOS bulk. Furthermore, comparing with the two-path double-precision FPA synthesized using LSI Logic's gflxp 0.11-μm CMOS library, it takes about 4.30% advantage in the critical path delay, and saves almost one-third area in the number of the individual cells.

This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

Due to its advantage of quantum resistance and the provable security under some worst-case hardness assumptions, lattice-based cryptography is being increasingly researched. This paper tries to explore and present a novel lattice-based public key cryptography and its implementation of circuits. In this paper, the LWE (learning with error) cryptography is designed for circuit realization in a practical way. A strategy is proposed to dramatically reduce the stored public key size from $m\cdot (n+l)2q$ to $m\cdot l\cdot log2q$, with only several additional linear feedback shift registers. The circuit design is implemented on Xilinx Spartan-3A FPGA and performs very well with limited resources. Only 125 slices and 8 BRAMs are occupied, and there are no complex operation devices such as multipliers or dividers, all the involved arithmetic operations are additions. This design is smaller than most hardware implementations of LWE or Ring-LWE cryptography in current state, while having an acceptable frequency at 111 MHz. Therefore, LWE cryptography can be practically realized, and its advantages of quantum resistance and simple implementation make the public key cryptography promising for some applications in devices such as smart cards.

This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network’s size and the input data vectors’ dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A $16\times 16$ SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one.

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. $16\times 16$ SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

Based on only MSP430F169 chip, a digital chaotic generator for a grid-like JERK chaotic system is designed, from which grid-like $6\times 6$ chaotic attractors are generated. By analyzing the nonlinear functions of the gird-like chaotic system, the saddle focal balance points are respectively extended in $x$,$y$ direction. According to the hardware requirements of MSP430F169 chip, using Euler algorithm to discretize the chaotic system, the values of 36 saddle focal balance points need to be recalculated. The numerical values of the focal balance points which are involving iterative operations are given by the proposed comparative piece-wise method, their analysis and numerical simulations are also performed. The software and hardware design ideas are given for implementation, the experiment results are verification of the feasibility of the scheme.

Several application-specific processor design approaches have been proposed and investigated to cope with the emerging flexibility requirements jointly associated with the maximum performance efficiency and minimum implementation area and power consumption. Dynamic scheduling of a set of instructions generally leads to an overhead related to instruction decoding. To mitigate this overhead, other approaches have been proposed using static scheduling of datapath control signals. In this context, No-Instruction-Set-Computer (NISC) concept have been introduced considering that a dedicated processor to a specific application does not need an instruction set especially when it is programmed by its designers and not by its users. In this paper, the hardware architecture design of flexible NISC-based architecture design dedicated for minimum mean-squared error (MMSE) linear detection is presented. The devised design, which is used in iterative turbo-receiver, fulfills the performance requirements of emergent wireless communication standards with throughput reaching that of LTE-Advanced. FPGA hardware implementation of the detector architecture achieves a maximum throughput of 115.8 Mega symbols per second for $2\times 2$ and 6.4 Mega symbols per second for $4\times 4$ MIMO systems for an operating clock frequency of 202.67MHz.

Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers.

A new chaotic system is proposed to generate multiscroll chaotic attractors. The major method used is for the step function to act as a nonlinear function. To prove that the proposed system can generate multiscroll chaotic attractors, the equilibrium point, the time domain waveform and the phase diagram of the proposed system are calculated. Finally, the design of the hardware circuit produces experimental results at a maximum of 8-scroll hardware. Theoretical analysis, simulation and hardware experimental results are fully matched, which further proves the existence of the proposed system and the physical realization. This provides the possibility for future applications in engineering.

Locally active memristors with multiple coexisting pinched hysteresis loops have attracted the attention of researchers. However, the currently reported multiple coexisting pinched hysteresis loops memristors are obtained by adding additional piecewise-linear terms into the original Chua corsage memristor. This paper proposes a novel locally active memristor by introducing a polynomial characteristic function into the state equation. The novel memristor has three coexisting pinched hysteresis loops, large relative range of active region and simple emulator circuit. The characteristics of the novel memristor such as power-off plot, coexisting pinched hysteresis loops and DC $V$–$I$ plot are studied. The memristor is used in a Chua chaotic system to investigate the effects of locally active characteristic on the chaotic oscillation system. Furthermore, the memristor emulator and chaotic system are designed and implemented by commercial circuit elements. The hardware experiments are consistent with numerical simulations.

This paper proposes a novel nonideal flux-controlled memristor model with a multipiecewise linear memductance function, which can be used to construct a memristive multi-scroll or multi-wing chaotic system. Importantly, arbitrary multi-double-scroll and multi-double-wing attractors can be generated depending on this memristor model directly and without the need to change the original nonlinear terms of the system. Another highlight is that the odd or even number of the double-scroll and double-wing attractors can also be freely controlled by the memristor model. To further illustrate these unique features, by introducing the memristor model into two classical chaotic systems, i.e. Jerk system and Lorenz system, multi-double-scroll and multi-double-wing chaotic attractors are obtained respectively. The formation mechanism of the multi-double-wing and multi-double-scroll attractors is also discussed. Moreover, the randomness of the chaotic binary sequences generated by the proposed memristor model is tested by the National Institute of Standards and Technology test suite. The tested results are better than those of the well-known Lorenz system. Furthermore, the corresponding circuits are constructed. The experimental results and the numerical simulations coincide well with each other, showing the effectiveness and feasibility of the proposed memristor model.

The symmetric Lyapunov exponents (LEs) are known to be an inherent property of continuous-time conservative systems. However, the research on this interesting phenomenon in a discrete-time chaotic map has not been reported. Thus, this paper presents an improved 2D chaotic map based on Gumowski–Mira (GM) transformation, which has a stable fixed point or an unstable fixed point depending on its control parameters. Furthermore, it can display symmetric LEs and an infinite number of coexisting attractors with different amplitudes and different shapes. To demonstrate the complex dynamics of the 2D chaotic map, this paper studies its control parameters related to dynamical behaviors employing numerical analysis methods. Then, the hardware implementation based on STM32 platform is established for illustrating the numerical simulation results. Next, the random performance of the 2D chaotic map is tested by NIST FIPS140-2 suite. Finally, an image encryption algorithm based on the 2D chaotic map is designed, and the results obtained reveal that the proposed chaotic map has excellent randomness and is more suitable for many chaos-based image encryptions.

In order to explore the phenomenon of coexisting attractors in complex chaotic systems, a multistable complex chaotic system is designed by using a cosine function and a control parameter to control the Sprott B system in this paper. The basic features of the complex chaotic system are analyzed from the perspectives of symmetry, dissipation, equilibrium points and stability. The analysis results indicate that the complex chaotic system is a symmetrical and dissipative system. It is particularly interesting to note that the system has infinitely many unstable equilibrium points, which generate infinitely many attractors. The dynamical characteristics of the complex chaotic system are evaluated through bifurcation diagrams, spectral entropy complexity and Lyapunov exponents spectrum. The dynamical evaluations illustrate that the system has complex dynamical performances, such as chaotic states, periodic states, especially infinitely many coexisting attractors. Then a chaotic circuit based on the complex chaotic system is designed and simulated by Multisim software. And the hardware circuit is implemented by using digital signal processor (DSP) platform. The hardware experimental results are consistent with the Multisim simulation results.