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Physical Unclonable Functions (PUFs) are probabilistic circuit primitives that extract randomness from the physical characteristics of a device. PUFs are easy and simple to implement and its random nature makes its behavior hard to predict and model. Most existing PUF designs are based on variation at the chip level and can not be implemented in a printed circuit board (PCB). Therefore, these PUFs can not be used to protect against counterfeit PCBs in a distributed supply chain. In this work, we propose a novel PUF design based on resistor and capacitor variations for low pass filters (LoPUF). We demonstrate the setup in a protoboard for different resistor-capacitor pairs (RC pairs) for reliable low pass filter PUF. Because of process variations, the voltage will be different at the same cut-off frequency for our proposed PUF. Finally, the output of the filter is connected to an inverter to measure the pulse width and best suitable pulses are used for ID generation based on our algorithm.

The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive hardware attack obtaining information from IC chips always violates the IP rights of vendors. This paper proposes a new security mechanism implanted ROM design to address the vulnerability to reverse energy attacks. Irreversible via in ROM layout transform triggered by reverse engineering completely changes the electrical properties and the physical structure of ROMs that determine the stored data. Newly-created patten will significantly increase the difficulty of reverse engineering, even lead the attackers to another working function mode. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Two widely used ROM scheme cases have been studied to test the design method and its effectiveness. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.

CCS Concepts: Security and privacy → Hardware reverse engineering; Hardware → Hard and soft IP

Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans.

Data security, privacy and authenticity are crucial in wireless data transmission. Low power consumption is the main requirement for any chip design targeting the Internet of Things (IoT) applications. In this research paper, a comparative study of eight authenticated encryption and decryption algorithms, selected from the “Competition for Authenticated Encryption: Security, Applicability and Robustness” (CAESAR), namely, ACORN, ASCON, CLOC, JOLTIK, MORUS, PRIMATEs, SCREAM and SILC, is presented. The FPGA and ASIC implementations of these eight algorithms are synthesized, placed and routed. Power, area, latency and throughput are measured for all algorithms. All results are analyzed to determine the most suitable algorithm for IoT applications. These results show that ACORN algorithm exhibits the lowest power consumption of the eight studied at the expense of lower throughput and higher latency. MORUS algorithm gives the highest throughput among the eight selected algorithms at the expense of large area utilization.

Floating point (FP) multiplication goes down in the scientific application when it sustains the subnormal inputs either in the implementation of software or hardware. Any high-level language executes the FP instructions in the graphics processing unit (GPU) and floating-point unit (FPU) for supporting the normalized numbers alone. In FP multiplication, execution times for normalized and subnormal numbers are not equal. Execution time variations create unintentional delay and data timing channels (DTCs). A circuit is proposed for floating-point multiplication to minimize the unintentional delay for the holistic support of subnormal numbers. In this proposed four-path FP multiplication, the circuit produces the four types of output in four paths having different delays for all cases of input combination. These four paths are establishing the DTCs. A maximum delay path is taken into account to combine and equalize the four paths into a single output path. Two levels of the control circuit combine the four paths to a single path for reducing the DTC effect. To evaluate the performance after path equalization, the proposed FP multiplier is implemented in Stratix-IV and Cyclone-IV FPGAs with a delay of 57.25 and 82.82 ns, respectively. Here, eight pipeline stages reduce the delay and improve the operating speed of the entire circuit. Stage delay and operating speed for this FP multiplier in both FPGA implementations are 12.44 and 16.86ns, and 153.19 and 116.78MHz, respectively.

In public-key cryptography, the RSA algorithm is an inevitable part of hardware security because of the ease of implementation and security. RSA Cryptographic algorithm uses many modular arithmetic operations that decide the overall performance of the architecture. This paper proposes VLSI architecture to implement an RSA public-key cryptosystem driven by the Residue Number System (RNS). Modular exponentiation in the RSA algorithm is executed by dividing the entire process into modular squaring and multiplication operations. Based on the RNS employment in modulo-exponential operation, two RSA architectures are proposed. A Verilog HDL code is used to model the entire RSA architecture and ported in Zynq FPGA (XC7Z020CLG484-1) for Proof of Concept (PoC). The Cadence Genus Synthesizer tool characterizes a system’s performance for TSMCs standard Cell library. Partial RNS (Proposed-I)- and Fully RNS (Proposed-II)-based RSA architectures increase the operation speed by 13% and 35%, respectively, compared with the existing RSA. Even though there is an increase in parameters like area, power and PDP for a smaller key size, the improvement in area utilization and encryption/ decryption speed of RSA for a larger key size is evident from the analysis.

Generating streams of true random numbers is a critical component of many electronic and information systems. The design of fully integrated, area and power efficient true random number generators (TRNGs) is a challenge. We propose a fully integrated, lightweight implementation that uses the random telegraph noise (RTN) of standard MOSFET as entropy source. It is not analog-intensive, and without traditional post-processing algorithms, the generated random bit sequence passes the National Institute of Standards and Technology (NIST) tests.

Physical unclonable function (PUF) is considered as a promising primitive for variety of security applications since its appearance, such as authentication, key generators and random oracle. With the fast development of Internet of Things (IoT), the requirement for low complexity, high power efficiency and enhanced security level of PUF becomes urgent. Meanwhile, the conventional PUF instances based on optical effect and semiconductors fail to meet the requirements due to poor scalability and sensitivity to attacks. This paper proposes a circuit design of PUF by utilizing the spin transfer torque magnetic random access memory (STT-MRAM). The performance of presented circuit design is thoroughly investigated from the aspects of uniqueness, reliability, uniformity, diffuseness, access speed and energy consumption. The simulation results show that the inter-Hamming distance can achieve 50% and the intra-Hamming distance can be reduced as low as 0%, resulting in perfect security. Meanwhile, the circuit behaves high immunity to environmental variations such as high and low temperature. With the rapid development of artificial intelligence, many powerful attack methods emerge. To defend against these attacks, the user reconfigurable function has been proposed. Moreover, design space including programming voltage, device parameters and thermal conditions has been explored to optimize the reliability of this function.

Physical Unclonable Functions (PUFs) are probabilistic circuit primitives that extract randomness from the physical characteristics of a device. PUFs are easy and simple to implement and its random nature makes its behavior hard to predict and model. Most existing PUF designs are based on variation at the chip level and can not be implemented in a printed circuit board (PCB). Therefore, these PUFs can not be used to protect against counterfeit PCBs in a distributed supply chain. In this work, we propose a novel PUF design based on resistor and capacitor variations for low pass filters (LoPUF). We demonstrate the setup in a protoboard for different resistor-capacitor pairs (RC pairs) for reliable low pass filter PUF. Because of process variations, the voltage will be different at the same cut-off frequency for our proposed PUF. Finally, the output of the filter is connected to an inverter to measure the pulse width and best suitable pulses are used for ID generation based on our algorithm.

The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive hardware attack obtaining information from IC chips always violates the IP rights of vendors. This paper proposes a new security mechanism implanted ROM design to address the vulnerability to reverse energy attacks. Irreversible via in ROM layout transform triggered by reverse engineering completely changes the electrical properties and the physical structure of ROMs that determine the stored data. Newly-created patten will significantly increase the difficulty of reverse engineering, even lead the attackers to another working function mode. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Two widely used ROM scheme cases have been studied to test the design method and its effectiveness. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.

CCS Concepts: Security and privacy → Hardware reverse engineering; Hardware → Hard and soft IP

Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.