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SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior.

Insulated gate n-channel enhancement mode InGaAs field effect transistors with the GdScO₃ high-k dielectric have been fabricated and studied. The low frequency noise was high indicating a high interface density of traps. Trap density and its dependence on the gate voltage have been extracted from the noise and conductance measurements.

Lanthanum cerium oxide thin films have been deposited on n-type (100) silicon wafers using the spin coating technique. The post-deposition annealing was performed over spin-coated films. The compositional studies were conducted by performing Fourier transform infrared spectroscopy, Energy dispersive X-ray spectroscopy, and X-ray diffraction. Ellipsometry was used to determine the thickness and atomic force microscopy was performed to understand the surface morphology of the deposited thin films. The effect of rapid thermal annealing at different temperatures over the structural and chemical properties of the LaCeO₂ thin films was observed. The FTIR spectra show the formation of silicates at the interface of the oxide and semiconductor, while XRD results show that the films become crystalline with increased annealing temperature. The refractive index was observed to be reduced with an increase in the annealing temperature and a minor reduction in the physical thickness as per the sample standard deviation of 0.2981nm.

In this paper, the interface charge densities ($D_{it}$) are studied and analyzed for ultra thin dielectric metal oxide semiconductor (MOS) devices using different high-k dielectric materials such as Al₂O₃, ZrO₂ and HfO₂. The $D_{it}$ have been calculated by a new approach using conductance method and it indicates that by reducing the thickness of the oxide, the $D_{it}$ increases and similar increase is also found by replacing SiO₂ with high-k. For the same oxide thickness, SiO₂ has the lowest $D_{it}$ and found to be the order of 10${}^{11}$cm${}^{-2}$eV${}^{-1}$. Linear increase in $D_{it}$ has been observed as the dielectric constant of the oxide increases. The $D_{it}$ is found to be in good agreement with published fabrication results at p-type doping level of $1\times 10^{17}$cm${}^{-3}$. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior.

Insulated gate n-channel enhancement mode InGaAs field effect transistors with the GdScO₃ high-k dielectric have been fabricated and studied. The low frequency noise was high indicating a high interface density of traps. Trap density and its dependence on the gate voltage have been extracted from the noise and conductance measurements.