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The modified version of Lee model code is used in numerical experiments for characterizing and optimizing neon soft X-ray yield ($Y_{\mathrm{\text{sxr}}}$) of the United Nations University/International Center for Theoretical Physics Plasma Focus Facility (UNU/ICTP PFF) device operated at 14 kV and 30 $\mu \mathrm{\text{F}}$. In our present work, the neon yield $Y_{\mathrm{\text{sxr}}}$ is improved with an optimized UNU/ICTP PFF device by computing the optimum combination of static inductance ($L_0$), anode length ($z_0$), anode radius ($a$) and cathode radius ($b$), keeping fixed their ratio ($c=b/a$) at 3.368, through a lot of numerical experiments at six operating pressures ($P_0$). At lower $P_0$ (e.g. 2.0, 2.5 and 3.3 Torr), the optimum $L_0$ value, together with the corresponding optimum combination of $z_0$, $a$ and $b$, is found to be 15 nH, whereas at higher $P_0$ (e.g. 4.0, 5.0 and 6.0 Torr), it is obtained as 10 nH. Though the computed maximum neon yield $Y_{\mathrm{\text{sxr}}}$ (57.2 J with the corresponding efficiency of 1.94%) is found at $P_0=4.0\mathrm{\text{Torr}}$, assuming an achievable range of incorporating low-inductance technology, the best optimum combination of $L_0$, $z_0$, $a$ and $b$ is found to be at $P_0=3.3\mathrm{\text{Torr}}$, resulting in the computed optimum neon yield $Y_{\mathrm{\text{sxr}}}$ of 54.60 J with a corresponding efficiency of 1.9%. This computed neon yield $Y_{\mathrm{\text{sxr}}}$ is about 11 times higher than the measured value $(5.4\pm 1\mathrm{\text{J}})$ at optimum $P_0=3.0\mathrm{\text{Torr}}$ of UNU/ICTP PFF. It is also observed that our computed neon yield $Y_{\mathrm{\text{sxr}}}$ is improved by around six times from the previously computed value, which was 9.5 J at the optimum $P_0=3.5$ Torr for optimum anode configuration of this machine. In addition, neon yield $Y_{\mathrm{\text{sxr}}}$ is obtained with our optimized combination of $L_0$, $z_0$, $a$ and $b$ at 11.5 kV and compared with the measured neon yield $Y_{\mathrm{\text{sxr}}}$ of the NX2 machine.

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be one useful figure of merit. It is shown that as the effective damping factor of a signal increases, an RC model is sufficiently accurate to characterize the waveform. The rise time of the input signal driving an RLC tree is shown to be a second factor that affects the relative significance of inductance. As the rise time of the input signal increases as compared to the effective LC time constant at a specific node within an RLC tree, the signal at this node will no longer exhibit the effects of inductance. It is demonstrated that a single line analysis to determine the importance of including inductance to characterize an interconnect line that is a part of a tree is invalid in many cases and can lead to erroneous conclusions. The error exhibited by single line analysis is due to the large interaction among the branches of the tree.

Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify the extraction of on-chip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance values. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the on-chip inductance is a slow varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values of the on-chip inductance to be determined with high computational efficiency.

In this paper, we introduce an implementation of a CCII-based grounded inductance operating in class AB. In order to get tunable characteristics of the design, a translinear CCII configuration is used as a basic block for its high level of controllability. A frequency characterization of the translinear CCII is done. In order to optimize its static and dynamic characteristics, an algorithmic driven methodology is developed ending to the optimal transistor geometries. The optimized CCII has a current bandwidth of 1.28 GHz and a voltage bandwidth of 5.48 GHz. It is applied in the simulated inductance design. We first consider the conventional topology of the grounded inductance based on the generalized impedance converter principle. Making use of the controllable series parasitic resistance at port X in translinear CCII, we design tunable characteristics of the inductance. The effect of current conveyor's nonidealities has been taken into account. A compensation strategy has been presented. It is based on the insertion of a high active CCII-based negative resistance and a very low passive resistance. The compensation strategy does not affect the inductance tuning process. Simulation results show that the proposed inductance can be tuned in the range [0.025 μH; 15.4 μH]. The simulated inductance has been applied in a fully integrated tunable high frequency band pass filter to illustrate the versatility of the circuit. The filter is electrically tunable by controlling the conveyor's bias current.

The main constraint that restricts wireless charging technology successfully applied in miniature medical electronic equipment is that the volume of the transmission coil is difficult to reduce. The printed circuit board (PCB) coil can take advantage of multi-layer wiring space to achieve the coil stack, achieving the purpose of increasing the relative magnetic flux, so that it could replace the traditional spiral coil to become the medium of wireless power transmission in the mini-medical electronic device.

In this paper, we analyzed several electrical parameters that could affect the 3D PCB rectangular coil inductance value based on the 3D PCB rectangular coil inductance computing method. Then we sort these influencing factors so that these results can help designers to design the 3D PCB coil. The conclusions are as follows: (1) number of layers, total number of turns have positive correlation with the self-inductance; metal width, substrate thickness, the pitch between adjacent turns have negative correlation with the self-inductance. (2) The sorting of influencing factors of the inductance is as follows: total number of turns$>$number of layers, the pitch between adjacent turns$>$substrate thickness$>$metal width.

This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46GHz for the tuning voltage of 0.3–1.5V. It consumes a low dc power ranging from 2.44mW to 4.79mW for the specified tuning range. The variation of phase noise ranges from $-83.03$dBc/Hz to $-78.65$dBc/Hz at 1MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of $-148.85$dBc/Hz with a differential output power of 1.8dBm at tuning voltage of 0.7V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.

This chapter focuses on applying surrogate models in a low noise amplifier (LNA), which is one of the main building blocks of modern communication circuits. In microelectronics, surrogate modeling has been shown to yield promising results to describe complex design surfaces. Using this feature, surrogate models can be established to extract specific design insights that enable the development of integrated circuits with higher performance and reliability. Examples of surrogate modeling in LNAs covered here explore the relationships between the voltage gain, noise figure, as well as input and output reflection coefficients. In particular, the variability of the voltage gain has been characterized through a surrogate model. Input parameters are composed of the gate, source, and drain inductors, along with their quality factors. Results confirm that highly accurate surrogate models for performance metrics such as voltage gain if an LNA can be built and employed in circuit design optimization.