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This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126$\mu$A from a 1.2V supply and occupies the 2184$\mu$m² area.

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1V supply. The circuit draws a total static current of 295$\mu$A and occupies 5000$\mu$m² of silicon area.

IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of $16\times 16$ pixels CdTe or CdZnTe pixelated detectors to build a low power micro-gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35$\mu$m process technology. Its power consumption is 800$\mu$W per channel. The energy range of the ASIC can be extended to 1.1MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7$\mu$s peaking time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2keV FWHM at 667keV (${}^{137}$Cs) on a single-pixel configuration. Meanwhile, we also measured 562eV and 666eV FWHM at 14keV and 60keV, respectively (${}^{241}$Am) with a 256 small pixel array and a low detection threshold of 1.2keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the linear energy transfer threshold above 110MeV/(mg/cm²). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high energy resolution. The chip is space qualified and flies on board of the solar orbiter ESA mission launched in 2020.