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This paper presented a multiplier-less memcapacitor emulator circuit that is implemented without using a memristor mutator. The proposed circuit is a charge-controlled memcapacitor built with analog blocks. Comparatively, this circuit uses fewer active–passive elements, where all passive elements are grounded. In addition, the most advantageous feature is its tuning which can be done externally by electronic means. Also, the proposed circuit layout has been drawn with minimum metal routing, optimum floor planning, and DRC and LVS checks. The circuit behavior is justified through various simulations in the Cadence Virtuoso-Spectre tool with 180-nm CMOS parameters, and the operating frequency of the proposed circuit is up to 4KHz. In addition, theoretical and simulated results are proven through experimental verification using off-the-shelf IC.

The hypercube as a parallel interconnection network has been of academic and engineering concern for tens of year due to its many merits. However, its increasing node degree is an obvious weakness. Some networks such as the cube-connected cycles (CCC) and the de Bruijn network have been proposed to overcome the increasing degree of the hypercube. In this paper, we present a new cost-effective network which outperforms the cube network. It can overcome the increasing degree of cube networks while keeping the advantages of the cube network such as logarithmic diameter, easy routing, optimal fault tolerance, and suitability for the ASCEND/DESCEND class of parallel problems. Furthermore, the proposed network achieves the logarithmic diameter with a very small constant node degree, 3 or 4.

In this paper we deal with the layout of Trivalent Cayley Interconnection Networks. Namely, we prove that a lower bound on their layout area is Ω(2^n-1× 2^n-1) and we exhibit some methods to lay these networks out in O(2^n-1× 2^n-1).

We piont out that these layout methods work for other networks decomposable into equal length cycles connected by following fixed rules.

In this paper we consider the problem of constructing planar orthogonal grid drawings (or more simply, layouts) of graphs, with the goal of minimizing the number of bends along the edges. We present optimal parallel algorithms that construct graph layouts with O(n) maximum edge length, O(n²) area, and at most 2n+4 bends (for biconnected graphs) and 2.4n+2 bends (for simply connected graphs). All three of these quality measures for the layouts are optimal in the worst case for biconnected graphs. The algorithm runs on a CREW PRAM in O(log n) time with n/log n processors, thus achieving optimal time and processor utilization. Applications include VLSI layout, graph drawing, and wireless communication.

Satisfiability modulo theories (SMT) is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT can be well tuned to solve several of the most intriguing problems in electronic design automation (EDA). Analog placers use physical constraints to automatically generate small sections of layout. The work presented in this paper shows that SMT solvers can be used for the automation of analog placement, given some physical constraints. We propose a tool that uses Microsoft Z3 SMT solver to find valid placement solutions for the given analog blocks. Accordingly, it generates multiple layouts that fulfill some given constraints and provides a variety of alternative layouts. The user has the option to choose one of the feasible solutions. The proposed system uses the quantifier-free linear real arithmetic (QFLRA), which makes the problem decidable. The proposed system is able to generate valid placement solutions for benchmarks. For benchmarks that have many constraints and few geometries, the proposed system achieves a speedup that is 10 times faster than other recently used approaches.

This paper presents results regarding the progress achieved in the design of a customized encrypted multiplexer cell. The focus of our interest is the no short-circuit dynamic differential logic method that demonstrates high immunity of a standard logic cell to the side channel attacks (SCAs). Three innovative solutions are examined and the best one is proposed for the encrypted multiplexer cell. Designed cells are realized to the layout masks level targeting the 350nm CMOS process. The post-layout simulations showed high resistivity to the SCA for all designed cells. The resistance to the SCA of the proposed design was statistically verified at the transistor level. The verification is performed using the Monte Carlo (MC) simulation in which widths and lengths of the transistor channel were varied according to the Gaussian distribution. The designed encrypted cell will be the part of a more complex crypto system for power consumption metering which should increase overall system’s data security.

In this paper, we present second generation current-controlled conveyor (CCCII)-based simple memristor circuit which exhibits a hard-switching voltage-current relationship. The proposed memristor circuit contains only single CCCII and single grounded capacitor that are attractive for the integrated circuit designers. The proposed memristor emulator has four main advantages: hard-switching behavior, not utilizing multiplier circuit, biasing current or voltage source (excluding DC current or voltage source), and being free of body effect for all transistors. Cadence Spectre Analog Environment with TSMC 0.18$\mu$m process parameters is used for all simulations. The memristive chip occupies only 81.85$\mu$$\text{m}\times 87.76$$\mu$m area. All simulation results are presented to demonstrate the performance of the proposed circuit by changing some parameters such as frequency, temperature, DC power supply voltages and process variations. Also, the robust performance of the proposed memristor is confirmed via Monte Carlo simulations. The simulation results for designed memristor are in accordance with theoretical memristive behavior.

A new operational transresistance amplifier (OTRA)-based third-order inverse bandpass filter (IBPF) is presented in this paper. To illustrate an application of the presented IBPF, the proposed configuration is used to implement a third-order quadrature oscillator (TOQO). Furthermore, the nonideal behavior of the proposed topologies has been examined using a single-pole model of the OTRA. It is perceived that for high-frequency applications, the effect of nonidealities may be eliminated through self-compensation. Passive sensitivities are computed and are found to be less than half, rendering proposed topologies insensitive to component variations. Phase noise study and frequency stability analysis have been carried out and found that the proposed TOQO enjoys good frequency stability. The proposed circuits’ workability is verified through an Analog Design Environment (ADE) Spectre tool provided by Cadence Virtuoso using 0.18 $\mu$m CMOS gpdk process parameters. Monte Carlo statistical analysis is also carried out to assess the prefabrication performances. Total harmonic distortion (THD) for the proposed IBPF is found to be less than 5%. Pre- and post-layout simulations are also included to affirm the theory. Excellent agreement among simulation results and theory is observed.

Quantum-dot Cellular Automata (QCA) is a nontransistor-based nanotechnology circuit design paradigm. The circuits are implemented by using cells having quantum dots and electrons. There are several cell configurations with varying combinations of electrons and quantum dots. But the widely used cells have the four-dot two-electron structure. Circuits are realized and validated by using QCADesigner. However, the layouts are developed manually by using this tool. Layouts are not entirely automated in QCA. Hence, in this work, the existing QCA tools and the different techniques proposed in the literature to improve the QCA layout generation are analyzed and a complete framework for QCA layout generation is proposed. It also explores the gap that needs to be filled to achieve a reliable CAD tool for QCA layout generation. In addition to that, to design circuits using rotated cells, design rules and cost functions are proposed. Novel circuits of multiplexer and D-flip-flop are also proposed using rotated cells. The proposed designs have better output polarization compared to other designs. Verification is done in QCADesigner.

Rooted trees abound in computing and it is often necessary to draw them for visualization and documentation purposes. In the classical convention for tree drawing, the tree is drawn in a “level” fashion, with nodes (represented by boxes) at depth k lying on a horizontal line at a distance of k units below the root. The parent — child relationships are represented by lines between the boxes. Several algorithms have been developed for constructing a compact layout of a tree in the classical convention.

In this paper we investigate algorithms for drawing trees according to two new conventions. In the inclusion convention, nodes are represented by boxes, and the parent — child relationship is represented by inclusion of one box in another. The tip-over convention again represents nodes as boxes, and, like the classical convention, represents the parent — child relationship by lines between the boxes; however, we allow siblings to be arranged vertically rather than horizontally.

For many of the cases which arise in visualization of trees (for example, binary trees with textual information at the leaves) we present polynomial time algorithms. However, the general problem of finding minimum size layouts for either of the new conventions is shown to be NP-hard.

This work studies layouts of the Butterfly network under the restriction that its input and output verticles are exposed, that is, are placed on the boundary of the grid. Avior et al. have shown that the minimal area of a layout of the n-input Butterfly, without the above restriction, is (1 + o(1))n²). The effect of this restriction on the area was left as an open question. This paper reveals that exposing the input and output vertices is essentially free. That is, it presents an exposed layout of the Butterfly having the same area as above. In this layout, the fractions of the input and output vertices assigned to each side of the grid are as follows when scanning the sides in a circular fashion: half of the inputs, half of the outputs, half of the inputs, and half of the outputs. We refer to such a layout as a -layout. The main technique employed in this layout is the reduction of the layout problem of the Butterfly to a certain layout problem of a complete bipartite graph. We use the same technique to produce a (I, 0, O, 0)-layout (inputs on one side and outputs on the opposite side) in area 2 + o(1))n². Finally, we show that the area of a -layout is greater than . Hence, this input-output configuration is more area-demanding than .

With the increase of circuit sizes and decrease of feature sizes it is expected that the overall performance of VLSI circuits will be more and more affected by signal propagation efficiency along interconnects. Wires can no longer be modeled as perfect conductors. Some electrical effects, previously considered as secondary, like for example parasitic loading introduced by wires, have to be taken into account at the layout design step. In this paper we address the problems of incorporating timing constraints into the placement and routing of integrated circuits. First, we introduce the timing models, formulate the problem and discuss graph models suitable for its analysis. Next, we give an overview of algorithms resulting in physical designs of improved performance in comparison to those whose objective is just the minimal layout.