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This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.

This paper presents FETs with vertically-stacked multiple quantum dot (QD) layers, comprising of GeOx cladded Ge quantum dots, serving as transport channel, floating gate in memory cell, and quantum dot gate that exhibit multi-state characteristics. The structures can be used as 8- and 16-state logic, a room-temperature alternative to sub-milliKelvin Si/SiGe qubits. In addition, they can be used as distributed NVRAMs with fast Write/Erase, SRAMs, and multi-state CMOS-X logic applications. Here, X symbolizes Multi-state CMOS compatible operations using SWS or QDC FETs or memories. The novelty includes: (i) coding of distinct states based on drain current changes in quantum dot channels via intra-sub band transitions and spatial location of carrier wavefunctions, (ii) integrating QDC-NVRAM cells with SRAM based cache, and multi-bit logic based computing.

This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.

This paper presents FETs with vertically-stacked multiple quantum dot (QD) layers, comprising of GeOx cladded Ge quantum dots, serving as transport channel, floating gate in memory cell, and quantum dot gate that exhibit multi-state characteristics. The structures can be used as 8- and 16-state logic, a room-temperature alternative to sub-milliKelvin Si/SiGe qubits. In addition, they can be used as distributed NVRAMs with fast Write/Erase, SRAMs, and multi-state CMOS-X logic applications. Here, X symbolizes Multi-state CMOS compatible operations using SWS or QDC FETs or memories. The novelty includes: (i) coding of distinct states based on drain current changes in quantum dot channels via intra-sub band transitions and spatial location of carrier wavefunctions, (ii) integrating QDC-NVRAM cells with SRAM based cache, and multi-bit logic based computing.