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Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Bogie is one of the most major mechanical part of railway train. Its security and reliability are of paramount importance. Since research in this field is still on the early stage, which focus on either mechanical structure without condition or binary coherent systems. A multistate network flow model has been proposed in this paper with consideration of components degradation level and functional interaction between them. Firstly, the structure and function of the bogie for CRH3 were made a detailed introduction. Then transmission paths of three types force on bogie were study to determine the network strcture. Different from other papers, arcs represent the components and nodes are the transitive relation. Arc capacity tends to be confirmed easily with utilization of performance deterioration of elements on bogie involved in force tranferring. Flow rate of each arc depends on both component' health status and the task it undertakes. Furthermore, the minimal paths (MPs) method and the recursive sum of disjoint products (RSDP) with ordering heuristics are used for system reliability calculation; and the relative probability importance of each basic component and system reliability with and without forehead information are given at last. The results show that the network flow model works well on CRH3 bogie, and can support as guidance of bogie system design, daily system operation and predictive maintenance.

We propose a method for computing the unavailability of a multistate-component system. This method is based on the construction of a Boolean model of the system, which may be represented in the form of a fault-tree. It is proved that the evaluation is always conservative, and very accurate when the probabilities of the component failures are low.

Fortunately traditional reliability theory, where the system and the components are always described simply as functioning or failed, is on the way to being replaced by a theory for multistate systems of multistate components. In this paper, we treat the consecutive k-out-of-n systems. Such systems have caught the attention of many engineers and researchers because of their wide range of application. We define a multistate consecutive k-out-of-n system: G as follows: Each component and the system can be in 1 of M + 1 possible states: 0, 1, 2, …, M. The system is in state ≥ j iff at least k_j consecutive components are in state ≥ j. The value of k_j can be different for different required minimum system state levels. We propose a method based on the combinatorial approach for computing the system's reliability and we give examples to illustrate this method.

This article is mainly to study the reliability evaluation in terms of MPs (minimal paths) for a multistate flow network G in which the capacities of each arc are real numbers. The transportation system from the source node s to the sink node t is one of such typical networks. Given the system demand d from s to t and MPs in advance, an algorithm is proposed first to find out all lower boundary points of level d (namely d-MPs here). The system reliability which is the probability that the system flow satisfies the demand d can be calculated in terms of such d-MPs. One example is presented to illustrate how all its d-MPs are generated. The computational time complexity in the worst case and average cases for such an algorithm is presented.

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.