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A new computer architecture called the Multithreaded Decoupled Architecture has been proposed for exploiting fine-grain parallelism. It develops further some of the ideas of parallel processing implemented in the Russian MARS-M computer in the 1980s. The MTD architecture aims at enhancing both total machine throughput and a single thread performance. To achieve this goal, we propose a two-level parallel computation model. Its low level defines the decoupled parallel execution of instructions within program fragments not containing branches. We will be referring to these fragments as basic blocks. The model’s high level defines the parallel execution of multiple basic blocks representing a function or procedure. This scheduling hierarchy reflects the MTD storage hierarchy. Together the scheduling and storage models allow a processor with multiple execution units to exploit several forms of parallelism within a procedure. The compiler provides the hardware with thread register usage masks to allow run-time enforcing of control and data dependencies between the high level threads. We present a possible implementation of the MTD-processor with multiple execution units and two-level distributed register memory.

We are pursuing the FUCE architecture project at Kyushu University. FUCE means FUsion of Communication and Execution. The main objective of our research is, as the name shows, to develop a new architecture that truly fuses communication and computation. The FUCE project develops a new on-chip-multi-processor and kernel software on it. We name the processor FUCE processor, and the kernel software as CEFOS (Communication and Execution Fusion OS).

The FUCE processor is designed as a network node processor to perform mainly switching/transmitting of messages/transaction and handling its contents. FUCE processor architecture is designed as a multiprocessor-on-chip to support the fine-grain multi-threading.

The kernel software CEFOS is also developed on the concept of multithreading. User and system processes are constructed as a set of threads, which are executed concurrently according to thread dependences.

Graph algorithms are becoming increasingly important for solving many problems in scientific computing, data mining and other domains. As these problems grow in scale, parallel computing resources are required to meet their computational and memory requirements. Unfortunately, the algorithms, software, and hardware that have worked well for developing mainstream parallel scientific applications are not necessarily effective for large-scale graph problems. In this paper we present the inter-relationships between graph problems, software, and parallel hardware in the current state of the art and discuss how those issues present inherent challenges in solving large-scale graph problems. The range of these challenges suggests a research agenda for the development of scalable high-performance software for graph problems.

The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensive use of global search operations. Previously, we developed a prototype associative SIMD processor that uses hardware multithreading to overcome the broadcast/reduction latency. In this paper we show, through simulations of the processor running an associative program, that hardware multithreading is able to improve performance by increasing system utilization, even for processors with hundreds or thousands of processing elements. However, the choice of thread scheduling policy used by the hardware is critical in determining the actual utilization achieved. We consider three thread scheduling policies and show that a thread scheduler that avoids issuing threads that will stall due to pipeline dependencies or thread synchronization operations is able to maintain system utilization independent of the number of threads.

Time series is acknowledged as one of the most common crucial data types in our daily lives. Among the time series mining tasks, rule discovery is important to provide valuable knowledge that brings us a profound insight view of relationships between different objects through time. One challenge is that when the number of objects and their lengths increase, it easily leads to a combinatorial explosion. Therefore, we propose a temporal inter-object association rule mining algorithm, NPTR, to discover new informative temporal inter-object association rules from time series and overcome the challenge with parallelization. Another remarkable point is that NPTR defines a concurrent approach by performing the frequent pattern mining process and rule mining one simultaneously. From the experiments on real-world data, NPTR returns the rules exactly with less time and memory costs than others do. Those rules can be further utilized for other tasks such as prediction, classification, and clustering.

In this paper a design thought that based on multi-thread, data buffer, communication techniques is proposed by which to improve real-time capability of communication for configuration software, a multi-thread model is designed to solve the problem of time-consuming I/O operation; The communication instructions in systematic will divide into two pieces of PRI, and cooperate with the data buffer queue of first-in first-out with PRI. It ensures that writing instruction can be executed first. An approach that combines homogeneous communication instruction and improves real-time capability of communication is presented in this paper. Finally, the results which are achieved with improved communication module show that the approach is valid on the running-platform.

A new method to realize hi-speed dynamic scanning curve is proposed based on Qt_E, in light of such problems in the embedded measurement system as Graphical user interface (GUI) takes up large space, has low operating efficiency and weak real-time performance. We analyzed the main characteristics of industrial equipment testing technology and added external plug-in library to basic library of Qt_E. Multi-threading technology is used that can simultaneously realize data collection, analysis and the function of parallel processing of the real-time display so as to ensure real-time performance and rapidity of GUI. The research experiment shows, hi-speed dynamic data display window was realized by making use of Qwt plug-in, fast and real-time, and can operate steadily in the environment of Linux embedded platform and provide good technical support for industrial equipment to realize hi-speed dynamic data display.