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This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.