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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

This paper presents a 65nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15dB reduction in the harmonic distortion for 20mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108$\mu$m² silicon area and consumes 0.43 $\mu$A from a 1.2V power supply.

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.

The increasing demand for low voltage, power efficient, high-speed analog-to-digital converters (ADCs) results in the improvement of speed and power of regenerative dynamic comparator. In this paper, a dual-tail dynamic comparator is used with two extra transistors in the latch stage. These extra transistors help in the increase of transconductance of the latch stage, which helps decrease the delay of the proposed comparator. Mathematical analysis is done for the proposed architecture; this gives the idea of reducing the delay of the comparator with an increase in the transconductance of the comparator. The simulation and layout of the proposed comparator are done on the Cadence software with 90nm CMOS technology. This proposed design is simulated with a 2GHz clock frequency at supply voltage of 1V. The proposed architecture consumes a power of 39.19$\mu$W and a delay of 143.12ps at 1V supply voltage, 5mV input difference voltage and 0.9V common mode voltage. The Monte Carlo simulation of the proposed architecture for power, delay, power delay product (PDP) and offset is also demonstrated in this paper. Process corner analysis is done for power, delay and PDP.

Most offset approximation algorithms for freeform curves and surfaces may be classified into two main groups. The first approximates the curve using simple primitives such as piecewise arcs and lines and then calculates the (exact) offset operator to this approximation. The second offsets the control polygon/mesh and then attempts to estimate the error of the approximated offset over a region. Most of the current offset algorithms estimate the error using a finite set of samples taken from the region and therefore can not guarantee the offset approximation is within a given tolerance over the whole curve or surface.

This paper presents new methods to globally bound the error of the approximated offset of freeform curves and surfaces and then automatically derive new approximations with improved accuracy. These tools can also be used to develop a global error bound for a variable distance offset operation and to detect and trim out loops in the offset.

Given a surface parametrization (non-necessarily birational) we provide a formula for computing the total degree of its generic offset. The formula essentially uses gcds and resultants of polynomials directly obtained from the input parametrization. In addition, it must be said that the formula is valid under the conjecture that not all offsets to a fixed rational (algebraic) surface pass though a fixed point; this was proved to be true in the curve case [Degree formulae for offset curves, J. Pure Appl. Algebra195(3) (2005) 301–335].

Kernel-based learning algorithms have been extensively studied over the past two decades for their successful applications in scientific research and industrial problem-solving. In classical kernel methods, such as kernel ridge regression and support vector machines, an unregularized offset term naturally appears. While its importance can be defended in some situations, it is arguable in others. However, it is commonly agreed that the offset term introduces essential challenges to the optimization and theoretical analysis of the algorithms. In this paper, we demonstrate that Kernel Ridge Regression (KRR) with an offset is closely connected to regularization schemes involving centered reproducing kernels. With the aid of this connection and the theory of centered reproducing kernels, we will establish generalization error bounds for KRR with an offset. These bounds indicate that the algorithm can achieve minimax optimal rates.

Loss function is the key element of a learning algorithm. Based on the regression learning algorithm with an offset, the coefficient-based regularization network with variance loss is proposed. The variance loss is different from the usual least quare loss, hinge loss and pinball loss, it induces a kind of samples cross empirical risk. Also, our coefficient-based regularization only relies on general kernel, i.e. the kernel is required to possess continuity, boundedness and satisfy some mild differentiability condition. These two characteristics bring essential difficulties to the theoretical analysis of this learning scheme. By the hypothesis space strategy and the error decomposition technique in [L. Shi, Learning theory estimates for coefficient-based regularized regression, Appl. Comput. Harmon. Anal.34 (2013) 252–265], a capacity-dependent error analysis is completed, satisfactory error bound and learning rates are then derived under a very mild regularity condition on the regression function. Also, we find an effective way to deal with the learning problem with samples cross empirical risk.

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

Rapid prototyping processes, like stereolithography, have gained wide industrial acceptance in recent years. The main advantage of rapid prototyping over conventional manufacturing processes is faster speed. Unlike material removal from a stock (as in machining), most rapid prototyping processes have to build the solid volume layer by layer. The tracing of the cross-sectional solid area in each layer is the most time consuming process. The process can be speeded up if the material volume to be traced can be reduced by extracting empty volumes in the original solid. With a Constructive Solid Geometry approach, the hollow solid generated by employing the negative solid offset technique is subjected to the problem of no interior support. A sub-boundary octree approach of generating thin shell solids with reinforced interior structuring is then proposed to re-solve the problem. As a result, the combination of the negative solid offset technique and the sub-boundary octree approach is proved to be success in generating thin shell solid with reinforced structuring that can be traced in a much faster speed. Algorithms have been implemented to demonstrate the validity of the proposed theory. Various testing models are produced by a Fused Deposition Modelling rapid prototyper and the results are supportive. The proposed theory can generate prototypes with good dimensional accuracy and surface flatness.