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Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

This paper presents a second-order bandpass filter for IF frequencies in the range of 500 kHz–2 MHz. By using a single G_m–cell as a biquad filter, considerable saving in area and power is feasible. Higher order structures can be achieved by cascading this second-order block. This G_m-C filter achieves a dynamic range of 37 dB for 1% IM3 in Bluetooth while dissipating only 10.5 mW from 3.3 power supply in 0.35 μm CMOS process. The on-chip indirect automatic tuning circuit sets the filter center frequency to an external reference clock.

The paper proposes a CMOS 65 nm 24 GHz wide-band frequency synthesizer with programmability on acquisition speed and supply voltage for low power application in 60 GHz millimeter-wave (mmW) wireless transceiver. The role of mmW phase-locked loop (PLL) is significant for supporting 7 GHz bandwidth across the four channels in IEEE 802.15.3c. The PLL is introduced with consideration of system specifications, as well as the design of individual block. In order to maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. A regulator is also adopted for supply noise suppression. The Voltage-Controlled Oscillator (VCO) covers frequency range from 24.2 to 29.3 GHz, with 19.1% tuning range. On top of the oscillator, a 1.2 V LDO (Low-Dropout Regulator) with 0.2 V dropout voltage is introduced to increase the immunity against low frequency noise fluctuation from supply. With the proposed structure, the PLL provides a loop bandwidth from 0.94 to 2.05 MHz. The phase margin is larger than 54° and the locking time can be adjusted 16% faster than nominal case. The VCO has better power supply rejection ratio (PSRR) of -48 dB, and Phase Noise of -94 dBc/Hz at 1 MHz frequency offset of 24 GHz.

A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible.

A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm². In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

Phase-locked loops (PLL) is a phase and/or frequency tracking system, widely used in communication and control systems. The sinusoidal multiplicative type PLL still remains a recurrent model, due the fact that its derivation is originated from the maximum likelihood approach. In this note, it is showed as a generalized product, called q-product, which can be used to implement the phase detector and improve some important parameters of the PLL system, as the block linearity and pull-in characteristics. Numerical examples are presented in order to illustrate the proposal.

A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented in this paper. The PFD consists of two identical building blocks. Each PFD block generates UP or DOWN signal and consists of $p$- and $n$-precharge stages connected in cascade. The proposed PFD circuit has no feedback path and has zero dead-zone in the phase characteristic, what is important in low jitter applications. It also has minimal blind-zone (extended input detection range) close to the limit imposed by the used CMOS technology. The PFD is designed in 0.13$\mu$m BiCMOS technology and has 1.8V supply voltage. The simulation results of blind-zone values are within the range from $1^{\circ }$ for 1GHz up to $4^{\circ }$ for 8GHz. This circuit can be used in applications for high-frequency and low-power delay locked loop and phase locked loop circuits, effectively.

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of $M$-stage ring-VCO with a resolution of $f_{\mathrm{\text{REF}}}∕(k\cdot 2M)$ in a time period of $k\cdot T_{\mathrm{\text{REF}}}$. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40nm CMOS process and operates from 1.2GHz to 3.6GHz with 8-phase outputs. The total lock time is less than 3$\mu$s including calibration and PLL closed-loop locking processes. Operating at 3.2GHz, the in-band phase noise is better than $-99.4$dBc/Hz and root-mean square (RMS) jitter integrated from 10KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5ps and $-68.5$dBc/Hz, respectively. The clock generator consumes only 3mW from 1.1V supply at high-frequency end and 1.6mW at low-frequency end. The active area is only 0.04mm² including on-chip loop filter and auto-calibration circuits.

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180^∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-$\mu$m CMOS technology with supply voltage of 1.8V. The output clocks with cycle-to-cycle jitter of 2.13ps at 1.6GHz. The phase noise of VCO is $-$137dBc/Hz at an offset of 100MHz and total power consumed by the proposed PLL is 2.63mW at 1.6GHz.

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ($g_m$) is the main dominant source of frequency and gain ($K_{\mathrm{\text{VCO}}}$) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates $\approx 3$ times variation in $K_{\mathrm{\text{VCO}}}$ across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5GHz is developed in 65nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum $K_{\mathrm{\text{VCO}}}$ variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4mW power from 1V power supply.

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

DSP (XC2267) is the main control chip which does the increment PI algorithms and realizes the voltage and current double closed-loop control. Three-phase thyristor rectifier method based on the phase self-adjusting of FPGA is proposed. A method for sweptfrequency start circuit is designed to implement the transition between the high-power and low-power. The invert system uses the compound control of improved PWM and frequency phase lock to improve the control accuracy and efficiency. Lastly, by using bench, the circuit is tested and the feasibility and effectiveness of the whole system are verified.

DSP (XC2267) is the main control chip which does the increment PI algorithms and realizes the voltage and current double closed-loop control. Three-phase thyristor rectifier method based on the phase self-adjusting of FPGA is proposed. A method for sweptfrequency start circuit is designed to implement the transition between the high-power and low-power. The invert system uses the compound control of improved PWM and frequency phase lock to improve the control accuracy and efficiency. Lastly, by using bench, the circuit is tested and the feasibility and effectiveness of the whole system are verified.