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This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm², and at room temperature, it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from $-$40${}^{\circ }$C to 125${}^{\circ }$C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/${}^{\circ }$C.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28$\mu$W power consumption in a standard 0.18$\mu$m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17ppm/^∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that $\sigma$/$\mu$ of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85mV with a temperature coefficient of 29.5ppm/^∘C for the temperatures ranging from $-55^{\circ }$C to 125^∘C at a supply voltage of 0.8V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8V to 5V at nominal temperature (27^∘C). A PSRR of $-$91.69dB is observed for the frequencies ranging from 1Hz to 10kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1Hz and 10kHz are obtained as 2.37$\mu$V/$\surd$Hz and 45.26nV/$\surd$Hz, respectively.

In this paper, we proposed a novel relaxation oscillator to address the frequency variation caused by the comparator delay. The conventional operational transconductance amplifiers (OTAs)-comparator is replaced with a Schmitt trigger to significantly reduce the delay. This Schmitt trigger is implemented by a differential structure operating in the subthreshold region to generate a proportional to absolute temperature (PTAT) hysteresis. Both the voltage reference and the current source are made PTAT as well. The proposed oscillator can be made ultra-low power and have excellent frequency stability over process, voltage and temperature (PVT) variation.

The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by $\sim$20dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to $V_{\mathrm{\text{DD}}}$ will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5dB PSRR improvement and 7.5% improvement in sensitivity to $V_{\mathrm{\text{DD}}}$. The proposed solution consumes 180nW power from 1V power supply voltage and occupies 3300$\mu$m² silicon area.