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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.

During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the fields of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background effects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background effects leads to a better Trojan-to-background-effect ratio and more (by about 1.7 times) Trojan detectability.

Three-dimensional integrated circuits (3D ICs) have recently garnered significant attention as a potential solution to the challenges posed by interconnect scaling in 2D ICs. However, the inclusion of an extra dimension and the introduction of through-silicon vias (TSVs) for interlayer connections have resulted in a significantly more complex compared to traditional 2D placement. In this paper, we propose an analytical framework for the stacked 3D ICs. Specifically, our approach involves the diffusion of standard and macro modules in the presence of wirelength and density forces, followed by a 2D mixed-size placement to optimize placement. To eliminate the overlap between macros, we perform legalization and fix them. The TSV insertions are then conducted, and we fix them in the center of the 3D net. Finally, legalization and detailed placement for cells are performed layer-by-layer. Furthermore, to improve the efficiency of the proposed framework, we propose a GPU-enabled acceleration strategy that accelerates the wirelength computation based on the deep learning toolkit PyTorch. Extensive experimental results on the standard-cell IBM-PLACE benchmarks and large-scale modern mixed-size (MMS) benchmarks demonstrate that the proposed framework outperforms state-of-the-art 3D placement methods.

During the physical design process, the second process of the quantum circuit design flow, using some optimization techniques after layout generation might be useful to improve the metrics or meet the design constraints. Focusing on this issue, this paper proposes an optimization technique using gate location changing to improve the latency of quantum circuits. The proposed technique uses layout and scheduling information to find critical paths and improve their latency by changing locations of the gates on the critical paths. Experimental results show that the proposed technique decreases the latency of quantum circuits up to 26% for the attempted benchmarks.

The reduction of technology size presents lots of new challenges to the physical design of VLSI chips, such as timing closure, routability, signal integrity, IR drop and antenna effect. This paper introduces the physical design flow of an ARM processor chip, specifically describes some of the key steps, such as floorplan, clock tree synthesis, design for manufacturability, and it can provide a reference for other similar designs. The chip using SMIC 130nm process includes ADC, PLL and a plurality of SRAM. The master clock frequency is 200M and the chip area is 4mm * 5mm.