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This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching amplifiers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the figure of merit (FoM). In addition, the integral nonlinearity (INL) and the differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18$\mu$m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.