Narrow Results

BAE Systems has developed a high power, high yield 70nm 6" 2-mil PHEMT MMIC process for frequencies up to 100GHz. Utilizing T-gate technology and 2-mil substrates, we have created a millimeter wave technology that produces excellent performance from Ka-band through W-bands. The device DC and RF characteristics have excellent uniformity across the wafer. In this paper, we report the 70nm device fabrication on 6-inch wafers and compare the DC and RF characteristics with its mature 0.1µm counterpart.

Novel circuit techniques and design approaches are proposed in this paper to build a controller dedicated to wireless power and data transmission systems used in the area of implantable devices such as sensors and neurostimulators. The aim of this controller is to regulate automatically the level of the power to be transferred and to modulate the carrier signals during data transmission. It includes several new integrated building blocks such as integrated pulse-width modulator (PWM), RF envelope detector, frequency-locked loop (FLL), and amplitude-shift keying (ASK) modulator and demodulator. CMOS 0.18 μm technology is used to implement this controller that operates at 1.8 V power supply and a frequency of 20 MHz. Preliminary postlayout simulation results prove that all the main blocks of the controller (the FLL, the PWM, and the ASKD) operate adequately. From simulation results, the time response of the system is estimated at 0.8 μs. The complete controller has been recently submitted for fabrication.

A novel adaptive current biased CLASS-A/shallow AB RF power amplifier is demonstrated in this paper. By theoretical deduction, a prototype is described to improve the linearity of a linear PA. With the realization on Jazz 0.35 μm SiGe HBT process and test verification, the novel adaptive current biased RF power amplifier shows 3 ~ 7 dB improvement of the ACPR at the output power of 19 dBm to meet the demand of CDMA IS95 spectrum mask without debasing the efficiency.

This paper presents a low power RF transceiver for 2.4 GHz ZigBee applications. The current reused inductor-less-load balun low noise amplifier (LNA) with quadrature mixer is proposed for area and power saving for low-IF receiver. The transmitter adopts power efficient power amplifier (PA) to improve transmitting efficiency. This RF transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves 6.5 dB noise figure (NF) and 20 dB conversion gain. The transmitter delivers maximum +3 dBm output power with PA efficiency of 30%. The receiver and transmitter front-end dissipate 1.9 mW and 5.3 mW at 1.8 V supply, respectively. The whole die area is 0.95 mm².

In this paper, a 1 mm × 1 mm fully integrated wideband dual-stage power amplifier (PA) for long-term evolution (LTE) band 1 (1920–1980 MHz) is presented. Fabricated in a 2 μm InGaP/GaAs hetero-junction bipolar transistor (HBT) process, the operating gain is observed to be 31.3 dB. The PA meets the minimum adjacent channel leakage ratio (ACLR) requirement of -30 dBc for LTE with 20 MHz wide channel bandwidth up to an output power of 30 dBm with the aid of a novel dual stage linearizer. Biased at low quiescent current of less than 100 mA with a headroom consumption of 3.5 V, the power added efficiency (PAE) is observed to be 38.29% at 30 dBm. With this high linear output power, the stringent requirement of antenna path loss is nullified. PA serves to be the first reported work to achieve 30 dBm linear output power at supply voltage of 3.5 V.

In this work, a novel and efficient approach is proposed to optimize linearity and efficiency of a power amplifier used in mobile communication applications. A linear and high performance push amplifier is designed and analyzed to extract design equations for an optimum performance. The proposed push amplifier has two sections; an analog section and a switching section. The analog section provides the required linearity and the switching section guarantees the satisfaction of the total efficiency level. Double power supply scheme is used in push amplifiers to enhance its performance. Two separate power supplies are employed for linear and switching sections of push amplifiers which have different voltage levels. The implemented circuit is simulated using HSPICERF with TSMC models for active and passive elements. The proposed power amplifier (PA) provides a maximum output power of 25 dBm and power added efficiency (PAE) as high as 51% at 2.5 GHz operation frequency. At 1-dB compression point, this PA exhibits output power of 25 dBm with 48% PAE and 4.5% error vector magnitude (EVM) which is appropriate for 64QAM OFDM signals.

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LPDSM) to reduce the quantization noise and to improve the coding efficiency. The simulation results show that for an uplink long-term evolution (LTE) signal with 1.92MHz bandwidth, 7.8dB peak-to-average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 41.72% in comparison to 9.7% CE for the Cartesian LPDSM transmitter. In the next step, the CE and bandwidth of the transmitter are improved at the same time by using the quantization noise reduction technique in the polar LPEDSM transmitter with parallel baseband. By using this combined technique in the four-branch transmitter baseband part for an uplink LTE signal with 7.68MHz bandwidth, 7.8dB PAPR, and an OSR of 32, the CE is improved from 42.59% to 55.86% with 40dB signal-to-noise-and-distortion ratio (SNDR) while the clock speed is only 61.44MHz which is four times lower than the clock speed requirement of the conventional transmitter baseband part to achieve the same SNDR.

A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45nm CMOS technology. The overall power consumption of the digital block is around 76mW at 800MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32dBm output power for a 5MHz input signal.

This paper introduces a methodology for implementing multi-band Doherty power amplifiers. Traditionally, a 90^∘ impedance inverter line is required in Doherty architecture. In this contribution, a generalized impedance inverter line is utilized to construct multi-band Doherty power amplifiers. A tri-band Doherty power amplifier operating at 1.15, 1.85 and 2.55GHz is designed to validate the proposed method. Measurement results show the fabricated Doherty power amplifier achieves 6dB output back-off drain efficiencies of 62.3%, 49.3% and 50.5% at 1.15, 1.85 and 2.55GHz, respectively. The peaking output power of the fabricated tri-band Doherty power amplifier is 43.2, 43.7 and 43.8dBm with drain efficiencies of 64.5%, 62.2% and 64.5% at three working frequency points, respectively. Furthermore, when the designed Doherty power amplifier is driven by a 20MHz wideband LTE signal with peak-to-average-power ratio of 6.4dB, adjacent channel power ratios of $-$29.4 and $-$57.1dBc are achieved before and after digital pre-distortion at 1.85GHz.

In this paper, a different dual-band asymmetric Doherty power amplifier (ADPA) with a novel dual-band bandpass filter (DBBPF) with quad-section stepped impedance resonators (SIRs) is presented. This specific DBBPF rejects the annoying frequencies of the second and third harmonics in the dual-band and contributes considerably to performance improvement of ADPA. This structure is confirmed with the design, simulation, implementation and testing of a 10 W GaN-based ADPA for global system for mobile communications (GSM) and worldwide interoperability for microwave access (WiMAX) applications at 1.84 and 3.5GHz, respectively. In the measurement results, the ADPA defines a drain efficiency (DE) of 63.7% with an output power of 35dBm and power gain is 14.2dB, and a DE of 47.5% with an output power of 34.5dBm and power gain is 10.4dB at the 9dB output power back-off (OBO) from the saturated output power in the two frequency bands. Linearity effects, applying 10MHz 16 QAM signal and a 5MHz WiMAX signal, display an adjacent channel leakage ratio of $-48.9$ and $-47.3$dBc with the average output power of 36.8/36dBm at 1.84/3.5GHz, respectively.

Wireless communication standard continues to evolve in order to fulfill the demand for high data rate operation. This leads to the exertion on the design of radio frequency power amplifier (RFPA) which consumes high DC power in order to support linear transmission of high data rate signal. Hence, operating the PA with low DC power consumption without trading-off the linearity is vital in order to achieve the goal of achieving fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the evolution of CMOS PA toward achieving a fully integrated transceiver solution is discussed through the review of multifarious CMOS PA design. This is categorized into the review of efficiency enhancement designs followed by linearity enhancement designs of the CMOS PA.

A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3ns, more than 500MHz of channel bandwidth and more than 20dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), $\dots$) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR $-$50dBc, at 10W LTE modulated PA output, antenna point and PA output power of 39.5dBm.

It has been widely validated that continuous working modes are powerful theories for designing broadband power amplifier (BPA). Theoretically, the conduction angle of all continuous-mode power amplifiers (PAs) is 180^∘ (class-B-biased). However, in practice, these PAs are always biased in class-AB condition. Thus, continuous-mode PAs biased in class-AB condition should be researched. This paper generalizes the theory of hybrid continuous mode (HCM) for implementing broadband power amplifiers. The intrinsic drain current waveform of HCM biased above the pinch-off point (conduction angle is larger than 180^∘) is first derived. Then, the impedance space of the generalized HCM (class-AB-biased) is explored and analyzed. The conclusion is that the generalized HCM possesses a shifted fundamental impedance space along with the enlargement of conduction angle. For validating the proposed theory, a broadband PA working over 1.6–3.0GHz is implemented. Experimental results indicate that the designed BPA achieves a saturation power of 40.3–42.7dBm and a drain efficiency of 64.3–74.4%.

A compact and efficient optical amplifier is demonstrated using an erbium–ytterbium-doped fiber amplifier (EYDFA) with a double-pass configuration. It uses only 3 m of doped fiber with 20 mW pump power. This forward-pumped amplifier achieves a maximum low signal gain of 37 dB and a corresponding noise figure of 5.5 dB. Compared with the backward-pumping double-pass EYDFA, the gain obtained is 7 dB higher, with a lower noise figure of 5.5 dB. In addition, the gain obtained in this study is 17 dB higher than that of a conventional forward-pumping single-pass amplifier, while its noise figure is only 0.5 dB higher. These results show that the forward-pumped double-pass design holds great promise in the development of practical and cost-efficient optical amplifiers which can be pumped by using LEDs or low cost laser diodes.

BAE Systems has developed a high power, high yield 70nm 6" 2-mil PHEMT MMIC process for frequencies up to 100GHz. Utilizing T-gate technology and 2-mil substrates, we have created a millimeter wave technology that produces excellent performance from Ka-band through W-bands. The device DC and RF characteristics have excellent uniformity across the wafer. In this paper, we report the 70nm device fabrication on 6-inch wafers and compare the DC and RF characteristics with its mature 0.1μm counterpart.