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Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

Quantum-dot Cellular Automata (QCA) based reversible logic is the utmost necessity to achieve an architecture at nano-scale, which promises extremely low power consumption with high device density and faster computation. This paper emphasises on the design of an efficient reversible Arithmetic Logical Unit (ALU) block in QCA technology. We have considered $3\times 3$ RUG (Reversible Universal Gate) as the basic unit, and also report a HDLQ model for RUG with 52.2% fault tolerance capability. Further, the reversible ALU has synthesized with reversible logic unit (RLU) and reversible arithmetic unit (RAU). We also demonstrate QCA implementation of RLU and RAU with lesser complexity and cell counts. The proposed ALU needs only 64 MVs (Majority Voters), which demonstrates 40% optimizations in the majority gate counts than the existing result. QCADesigner-2.0.3 is used to verify the proposed designs.

Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems. It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption. The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters. It is also a potential technology for low force and high-density memory plans. Large memory designs in QCA show unique features because of their architectural structure. In QCA-based architectures, memory must be maintained in motion, i.e., the memory state has to be continuously moved through a set of QCA cells. These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank. However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy. Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field. Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM). Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided.

Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.

Quantum-dot cellular automata (QCA) is an advanced nanotechnology. It is applied to delineate nanoscale technology-based logic circuits. It can potentially be replaced the complementary metal oxide semiconductor (CMOS) technology. This paper proposes an optimal and single clocked multiplexer (Mux) circuit, which is made with the help of 12 number of QCA cells in QCA nanotechnology. The proposed Mux circuit is designed in such a way that it can be used easily for the design of the demultiplexer (DeMux) and data flip-flop (DFF) circuits. The proposed Mux is easily converted to DeMux by exchanging the input and output terminals only. The effectiveness of the proposed Mux, DeMux, and DFF is examined with the designs that are similar and available in literature using the QCA Designer-E and QCA Pro tools. The design of the proposed Mux is 89.06% fault-tolerant and has decreased the quantum cost by 62.50% as compared to best reported design. Energy measurement plays a key role when designs are operating at nanoscale level. Energy approximation is done with the help of the QCA Pro tool. The proposed designs are more energy efficient compared to the existing works.

The purpose of this research is to understand: (1) the main themes that appear to contribute to entrepreneurial success, (2) the various combinations of antecedents that can lead to entrepreneurial success, and; (3) the role that travel plays in entrepreneurial success. We first use a qualitative methodology to assess the themes that emerge in our conversations with 14 highly-successful Canadian entrepreneurs. The main categories that emerged from our interviews that contribute to entrepreneurial success involve: learning, travel, adversity quotient, and mentorship. From these results, we conduct a qualitative comparative analysis (QCA) and find that the input variables that were most important to entrepreneurial success were: learning, experiencing failure, learning from mentors, and adversity quotient. The contributions to knowledge of this research are twofold. First, we show that travel is an important construct to entrepreneurial success, which is significant as travel has largely been omitted from the entrepreneurship literature. Second, we show that entrepreneurial success is dependent on a complex combination of variables of varying levels of importance.

The significant physical challenges of Complementary Metal Oxide Semiconductor (CMOS) technology drives it on the brink of ultimate limit. With the surfacing of tremendous research findings, Quantum dot cellular automata (QCA) has emerged as a new technology in nanoscale era as a viable alternative to CMOS technology. Besides its wide acceptance, QCA-based nanoscale circuits are highly susceptible to huge fault/error rates. Thus, the fault tolerance and testability have become the utmost necessity for ensuring reliable QCA circuit. Toward this direction, conservative logic plays a vital role to achieve such reliability. In this paper, a Conservative Full Adder (CFA) is proposed with a simplified testable logic to detect the internal fault in the circuit. A simple majority–minority-based testing logic in the circuit is augmented for the detection of conservative (bit preserving) nature. Besides the testable feature, the full adder is chosen for its versatility in Arithmetic and Logic Unit (ALU) synthesis. Experimental result establishes the superiority of the proposed logic in terms of design capability as well as testability. Also, a comprehensive analysis of energy dissipation is performed to ensure the robustness of the proposed testable conservative adder. The QCA layout design and functional verification of the design are performed using the QCADesigner tool and Hardware Description Language for QCA (HDLQ) tool, respectively. The QCAPro simulator is used to evaluate the energy dissipation of the circuit.

The use of quantum-dot cellular automata (QCA) technology for the design of logic circuits has shown to increase data transfer rates up to 2 THz. In QCA technology, circuits are designed to have an ultra-small feature size as well as ultra-low power consumption. Grain-128 is one of the best stream ciphers in the final list of the eSTREAM project. In this paper, we have designed and simulated the main blocks of this algorithm including XOR gate, linear-feedback shift register (LFSR) and nonlinear-feedback shift register (NLFSR) using QCA technology. The designs of these blocks using the QCA Designer simulator are given and the main factors such as area, complexity and delay are estimated. Furthermore, ModelSim software is used to simulate HDLQ model of the QCA Grain-128 stream cipher algorithm. The results indicate that the main parameters of the proposed Grain-128, such as area and throughput, are improved as well.

Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in the field of ALU design. This paper provides the comprehensive, systematic and detailed study and survey of the state-of-the-art techniques and mechanisms in the field of QCA-based ALU designing. There are three categories in which QCA plays a role: ALU, logic unit (LU) and arithmetic unit (AU). Each category presents the important studies. In addition, this paper reviews the major developments in these three categories and it plans the new challenges. Furthermore, it provides the identification of open issues and guidelines for future research. Also, a Systematic Literature Review (SLR) on QCA-based ALU, LU and AU is discussed in this paper. We identified 1,960 papers, which are reduced to 26 primary studies through our paper selection process. According to the obtained results from 2001 to 2015, the number of published articles are very high in 2014 and low in 2005 and 2009. This survey paper also provides a discussion of considered mechanisms in terms of ALU, LU and AU attribute as well as directions for future research.

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

This study demonstrates the development of an innovative $n$-bit less power ripple carry incrementer (RCI) and decrementer (RCD) circuit, respectively, devised using quantum dot cellular automata (QCA). In order to increment or decrement two numbers, RCI and RCD are essential. With a revised configuration of the AND gate, half adder, and XOR gate circuit, the suggested ripple carry incrementer and decrementer circuits are realized. Modern designs for the XOR and half adder are contrasted with these freshly created ones. Circuits are designed using QCA designer 2.0.3. The 4-bit RCI, 8-bit RCI, and 16-bit RCI as well as 4-bit RCD, 8-bit RCD, and 16-bit RCD simulation results are compared to the theoretical findings.

The quantum-dot cellular automata (QCA) is popular nanotechnology to process at deep sub-micron levels. In recent years, in QCA technology, numerous multi-layer circuits of adders and subtractors have been developed. However, little attention has been made to the QCA circuit’s instantiation of the subtractors schemes. This paper gives a three-layered subtractor with simple access to inputs and outputs as an essential block in QCA technology. This design was created, optimized, and simulated using QCADesigner-E. The results revealed that the suggested proposal effectively reached a higher level of efficiency, speed, and cost, owing primarily to the use of the three layers’ design. Also, this architecture offers a platform to access the input and output lines more easily. The multi-layer crossover technique is used to build this design. According to the simulation findings, the suggested subtractor in QCA technology employs 22 QCA cells. The simulation findings demonstrated that the proposed design surpasses the majority of previous results in the literature.