Narrow Results

Blind quantum computation (for measuring the client Alice) protocol changes the role of the client from state preparation to measurement. In order to further save the quantum cost and delegated cost of Alice, two protocols are proposed to complete a certain single-qubit gate with fewer measurements and qubits while remaining loss tolerant in this paper. Finally, the protocols are feasibility from three aspects: blindness, correctness and universality.

Homogeneous Boolean functions have many applications in computing systems, e.g., cryptography. This paper presents a factorization algorithm for reducing the quantum cost of the reversible circuits for that class of Boolean functions. The algorithm reduces the multi-calculation of any common parts of the circuit. This allows Homogeneous Boolean related applications to be implemented efficiently on novel computing paradigms such as quantum computers and low power devices.

In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.

The reversible circuit synthesis problem can be reduced to permutation group. This allows Schreier–Sims algorithm for the strong generating set-finding problem to be used to find tight bounds on the synthesis of 3-bit reversible circuits using the NFFr library. The tight bounds include the maximum and minimum length of 3-bit reversible circuits, the maximum and minimum cost of 3-bit reversible circuits. The analysis shows better results than that found in the literature for the lower bound of the cost. The analysis also shows that there are 2460 universal reversible sub-libraries from the main NFFr library.

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2^m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

Reversible logic has gained its importance in the field of low power digital design. In any digital system, the comparator plays an important role in determining whether the two referenced numbers are either equal, greater or lesser. This work deals with optimization of existing reversible comparator designs and also proposes a new multiplexer-based logic for the design of reversible comparator along with design methodology for $n$-bit comparators. The proposed design is optimized for multiple performance parameters compared to the existing state-of-the-art designs. The proposed multiplexer-based design has 51.9% improvement in quantum cost, 50% in garbage outputs and 62% in ancilla inputs. These optimized designs find application predominantly in the field of quantum computing for low power signal processing, parallel computing, memories, digital system design and multi-processing.

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the $n$-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm² area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in nanocircuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a new $5\times 5$ reversible block and then its quantum realization is given using the Miller et al. method. In the following, an effective reversible design of D flip-flop is introduced using the proposed reversible block. Finally, four types of reversible shift register including serial-in to parallel-out (SIPO), parallel-in to parallel-out (PIPO), parallel-in to serial-out (PISO) and shift counter are proposed using the proposed reversible flip-flop. The evaluation results show that the proposed circuits are superior compared to the existing designs in terms of quantum cost (QC).

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an $(n\times n)$ reversible circuit implemented with $k$-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size $(n+2)$ to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

In this paper, a Quantum-Dot Cellular Automata (QCA)-based $D$-flip flop is designed with low quantum cost to propose a 3-bit sequence detector which detects a bit pattern 101 in both overlapping and non-overlapping forms. Initially, a level to edge-triggered clock converter is proposed to convert clock signal levels into edge defining signals. Later, $D$-flip flops of both level and edge triggered clock inputs are developed. Compared with the recently reported designs in the literature, it is observed that the quantum cost of the proposed $D$-flip flops is decreased by more than 28% with a cell count of 34, which in turn defines the low area too. Also, latency of the same is reduced by one-fourth with a value of $1.25\times 10^{-12}$ s. As far as the sequence detector is concerned, it is smaller in size at 0.16$\mu$m² than the existing sequential circuits with a reduction in area and quantum cost by 30%. Further, from the bit stream it detects, the proposed sequence detector can also be used as negative pulse detector and interrupt handler circuit in the future QCA-based digital systems to detect the external interrupts.

Since non-permutative quantum gates have more complex rules than permutative quantum gates, it is very hard to synthesize quantum logic circuits using non-permutative quantum gates, such as controlled-square-root-of-NOT gates (CV∕CV⁺ gates). In the efficient synthesis algorithm, direct use of quantum non-permutative gates should be avoided. Rather, the key method is to use quantum gates to create new permutative quantum gates that then replace non-permutative quantum gates. This method assumes the library of quantum gate primitives are constructed so as to have the lowest possible quantum cost. In this paper, we first propose some new CV∕CV⁺-like gates, i.e. controlled-kth-root-of-NOT gates where k = 2,4,8,…, and give all corresponding matrixes. Further, we also present a novel generic method to quickly and directly construct this new optimal quantum logic gate library using CNOT and these non-permutative quantum gates. Our method introduces new means to find permutative quantum gates with lower quantum cost.

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh$-$Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

The development of nanoscale technologies has come from the downsizing of electronic equipment and the inadequacy of CMOS innovation resulting from hybrid circuit establishment and its failure to respond to nanoscale. Quantum-based technologies, like quantum-dot cellular automata (QCA), are likely to succeed the present technologies due to their incredible benefits, like faster processing, smaller footprints and ultra-low energy usage. In arithmetic and comparison circuits, the fundamental gate is frequently used. Arithmetic logic circuits centered on OR, AND and NOT logic gates have a low design complexity. To obtain complicated logic gates, several architectures have been proposed in the QCA. This work offers a QCA composite gate that achieves all critical digital logic gates, including Inverter, OR, AND, NAND, NOR and exclusive gates like XOR and XNOR. All basic logic is generated in a single unit with this architecture. Only 0.09$\mu$m² of area, three three-input majority gates, one XOR, three Inverters, and 0.5 clock zones were required for the suggested circuit. As a result, a decrease of 33% in cell count is achieved compared to the previous systems. The design is evaluated and the dissipated energy is analyzed. For the research on power dissipation, the QCADesigner-E simulator is used to verify the final result. The simulation outcomes show that the suggested layout is advantageous over earlier constructions regarding the area, number of cells, clock phases and cost.