Narrow Results

Reconfigurability is a desirable characteristic in parallel computer architecture that supports the structural parallelism inherent to multiple parallel algorithms. This paper presents a novel approach to achieve reconfigurability via a multiple-domain wavelength-division multiplexed optical interconnection network. A network structure is defined to host a set of point-to-point guest interconnection topologies. Fast complete reconfiguration takes place by re-labeling node identifiers and re-tuning receiver filters according to a local table at each node. For a network of size N, the connecting fiber complexity is O(N), the same order of the link complexities of the individual topologies. The proposed network avoids the possible edge dilation, congestion, and cumulative switching latencies associated with previously proposed approaches.

A runtime system for implementation of image processing operations is presented. It is designed for working in a flexible and distributed environment related to the software architecture of a newly developed UAV system. The software architecture can be characterized at a coarse scale as a layered system, with a deliberative layer at the top, a reactive layer in the middle, and a processing layer at the bottom. At a finer scale each of the three levels is decomposed into sets of modules which communicate using CORBA, allowing system development and deployment on the UAV to be made in a highly flexible way. Image processing takes place in a dedicated module located in the process layer, and is the main focus of the paper. This module has been designed as a runtime system for data flow graphs, allowing various processing operations to be created online and on demand by the higher levels of the system. The runtime system is implemented in Java, which allows development and deployment to be made on a wide range of hardware/software configurations. Optimizations for particular hardware platforms have been made using Java's native interface.

In current System-on-Chip (SoC) design, the main engineering trade-off concerns hardware efficiency and design effort. Hardware efficiency traditionally regards cost versus performance (in high-volume electronics), but recently energy consumption emerged as a dominant criterion, even in products without batteries. "The" most effective way to increase HW efficiency is to exploit application characteristics in the HW. The traditional way of looking at HW design tends to consider it a time-consuming and tedious task, however. Given the current lack of HW designers, and the pressure of time-to-market, clearly a desire exists to fine-balance the merits and effort of tuning your HW to your application. This paper discusses methods and tool support for HW application-tuning at different levels of granularity. Furthermore we treat several ways of applying reconfigurable HW to allow both silicon reuse and the ability to tune the HW to the application after fabrication. Our main focus is on a methodology for application-tuning the architecture of DSP datapaths. Our primary contribution is on reusing and generalizing this methodology to application-tuning DSP instruction sets, and providing tool support for efficient compilation for these instruction sets. Furthermore, we propose an architecure for a reconfigurable instruction-decoder, enabling application-tuning of the instruction-set after fabrication.

Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing.

This paper aims to improve the autonomous operational capabilities of spacecraft. For a complex system with physical coupling and flexible attachments, an autonomous reconfiguration strategy based on reconfigurability evaluation is proposed. First, a quantitative evaluation index for reconfigurability is given based on operator theory to fully exploit the potential of system reconfigurability under resource constraints. Then, specific requirements and evaluation methods for autonomous reconfiguration are proposed in accordance with the results, thereby providing a theoretical reference for the design of reconfiguration strategy methods. Thus, reconfigurability is maximized from the design point of view. Finally, the validity and correctness of the method are verified by simulation.

Recent trends on wireless technologies as well as on software progress make the reconfiguration of wireless terminals not only an interesting feature but also an achievable one. This paper presents the motivation leading to the need of reconfigurable equipment management. A simple architecture of such equipment is given to allow the reconfiguration and its management. This architecture is based on the use of communicating agents, which provides a way for negotiating the appropriate configuration between the network and the terminal as well as easy context discovery or autonomous decision handling. Experiments based on a prototype shows that this agent-based approach is a good candidate for managing fully reconfigurable systems.