Narrow Results

In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45 nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

Flexible resistive switching memory devices based on graphene oxide (GO) polymer nanocomposite were prepared on flexible substrate to research the influence of bending on resistive switching behavior. The devices showed evident response in resistive switching memory characteristics to flexible bending. The 2000 cycles flexible bending leads to the switch of resistive switching memory characteristic from write-once-read-many time memory (WORM) to static random access memory (SRAM). Both WORM and SRAM memory properties are all repeatable, and the threshold switching voltage also showed good consistency. The resistive switching mechanism is attributed to the formation of carbon-rich conductive filaments for nonvolatile WORM characteristics. The bending-induced micro-crack may be responsible for the partial broken of the electrical channels, and may lead to the volatile SRAM characteristics.

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO₂ quantum dots. The work performed here builds off previous works performed with Si/SiO₂ dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

This paper investigates the underlying physics of a SRAM device utilizing three-state Quantum Dot Gate (QDG) FETs by building up the physics from the general QDG-FET, its relation to the QDG-Inverter, and ultimately, the QDG-SRAM. The resulting equations from the exploration of the device physics were utilized to create a simulation within SIMULINK. From the simulation, it was found that in addition to being able to store the “1” and “0” states that are customary for an SRAM device, there is also the ability to store an intermediate state and a pseudo-state as a result of the intermediate state, allowing for the possibility of a 2-bit SRAM device in the same spatial constraints of a conventional SRAM unit cell. Additionally, the experimental results of the QDG-SRAM half-cell and the implications of utilizing a 4 state device to create either a 4 state SRAM cell or a 6 state SRAM cell with two pseudo-states are also discussed.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) n-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.