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Modern wireless communication poses the requirements of fast settling time, small channel width, and low phase noise to frequency synthesizer. ΣΔ fractional-N frequency synthesizer is widely adopted due to its excellent characteristics in these aspects. This paper presents a number of system issues and design considerations/tradeoffs which are involved in the design of such a frequency synthesizer from the system point of view. These considerations include selection of loop parameters, choice of key building blocks, and critical system performance issues like spurious tones, quantization noise, in-band phase noise, out-of-band phase noise, and frequency accuracy/resolution. Finally, the future possibilities are briefly analyzed.

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.