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For the requirement of power management controller chips, a wide supply range bandgap voltage reference circuit is presented. The preregulated circuit based on the regulation characteristic of zener diode extends the supply range and increases power supply rejection ratio (PSRR). Compensated by the base-emitter voltage (V_BE) linearization technique, the temperature stability of the bandgap circuit is improved further. The proposed circuit is implemented in a 0.4 μm bipolar CMOS DMOS (BCD) process and Spice simulation has been done for validation. The results of simulation and test show that the supply range of this circuit can reach 7.2 V to 40 V and 159 μV/V of supply voltage dependence; the temperature coefficient is just 3.5 ppm/°C over a wide temperature of -40°C to 125°C and PSRR is up to -94 dB at 1 kHz. For the perfective performance, this circuit can be used in wide temperature and wide supply range integrated circuit design.

This paper proposes a novel second-order temperature-compensated CMOS current reference which exploits a new self-biased current source for first-order temperature compensation and a resistor-free widlar current mirror for second-order temperature compensation. Moreover, by deriving the temperature coefficient (TC) of the reference current, the temperature compensation condition equations together with a design method of minimizing the thermal drift in a required temperature range are presented. Based on these, the circuit is designed in a standard 0.18 μm CMOS process and achieves a very low TC of only 16.9 ppm/°C in a temperature range between -40°C and 120°C, with 1 μA reference current at 27°C. Besides, the current reference can operate at supply voltage down to 1.3 V, with a good supply regulation of 0.5%/V. At 27°C, its power consumption is 8.93 μW.

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, $-$80dB power supply rejection (PSR) @1kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard $0.18\mu$m CMOS process, consuming 50$\mu$A at 25${}^{\circ }$C with a supply voltage of 3.3V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18ppm/${}^{\circ }$C over the temperature range from $-40^{\circ }$C to 120${}^{\circ }$C. Monte Carlo simulation and Experimental Results validate the design.

This paper presents a novel low-voltage bandgap reference with improved power supply rejection (PSR). The proposed circuit adopts a complementary loop locking approach for stabilizing the drain-source voltages of the current mirrors, which gives rise to a boost of the PSR performance by more than 30dB over $-20$–110^∘C and at 1-V supply. An analysis shows that the PSR of the proposed bandgap reference is typically characterized with its insensitivity to temperature variations. The circuit is designed with a commercial 0.18-$\mu$m CMOS process. The experiment results of Monte Carlo simulation demonstrate that the average PSR with 1-V supply is $-106$dB at DC and is $-93.8$dB at 1kHz (attained under a room temperature condition of 27^∘C). And the temperature coefficient of the DC-based PSR is about 0.83%/^∘C at 1-V supply, significantly decreased by three–six folds compared to other conventional designs. The quiescent current consumed is only about 13.5$\mu$A.

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about $-111$dBc/Hz at 10MHz offset frequency. Frequency changes less than $113.06\mathrm{\text{ppm}}{∕}^{\circ }\mathrm{\text{C}}$ in the temperature range of $-40^{\circ }$C–$100^{\circ }$C. The clock generator consumes 0.657mW of power. Results show improvement in comparison to the previous works.

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18$\mu$m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27^∘C on driving a load of 1mA along with a Power Supply Rejection Ratio (PSRR) of $-117$dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064mm² and offer a TC as low as 1.7077 ppm/^∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85mV with a temperature coefficient of 29.5ppm/^∘C for the temperatures ranging from $-55^{\circ }$C to 125^∘C at a supply voltage of 0.8V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8V to 5V at nominal temperature (27^∘C). A PSRR of $-$91.69dB is observed for the frequencies ranging from 1Hz to 10kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1Hz and 10kHz are obtained as 2.37$\mu$V/$\surd$Hz and 45.26nV/$\surd$Hz, respectively.

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

The mean-square radius of gyration 〈S²〉, the mean-square dipole moment 〈D²〉, the mean-square end-to-end distance 〈R²〉 and their temperature coefficients of unsymmetrical disubstituted poly(methylphenylsiloxane) (PMPS) chains, as a function of stereochemical structure, confomational energies and length of polymers, were studied by using an improved configurational-confomational statistical method based on the rotational-isomeric-state theory. It is found that the increase in isotacticity of PMPS chains causes a significant decrease in the unperturbed dimensions and increase in their temperature coefficients. This correlation of the properties of PMPS and its stereochemical structure is different from that of vinyl monosubstituted polystyrene and disubstituted poly(α-methylstyrene) chains. Dependence of the characteristic ratio of 〈S²〉 on conformational energy E_ω′ of C₆H₅…C₆H₅ four-bond interactions increases markedly with the degree of isotacticity increasing, the dependence on the conformational energy E_δ and dE_σ decreases with increasing the degree of isotacticity. It is also found that the characteristic ratios of 〈R²〉 and its temperature coefficients are in agreement with corresponding experimental results in the degree of isotacticity of about 0–40%. Moreover, the C₆H₅…C₆H₅ four-bond interactions play a dominant role in regard to the dimensions of high syndiotactic chains. In addition, the effect of large side groups on unperturbed dimensions is investigated further by the improved expressions of 〈S²〉.

This paper proposes a current-mode low bandgap reference voltage circuit with low temperature coefficient and independent of supply voltage for applications to low voltage power management integrated circuits. This proposed circuit is design and implemented using the TSMC 0.18μm 1P6M CMOS process technology. Based on simulated and measured results , the chip size is 0.58303 × 0.50206mm² with power dissipation about 0.43mW , and the operation temperature range form − 20°C to 100°C with temperature coefficient about 15 ppm/ °C. The chip supply voltage can from 1.0V to 1.8V with PSRR about 85dB, and its output reference voltage can stable at 0.59mV.