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Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.

Studying temperature effects on defect behaviors during thermal annealing is significant for understanding the performance degradation and recovery of semiconductor devices under irradiation. We systematically studied temperature effects on annealing crucial deep-level defects in neutron-irradiated silicon, by developing a multiscale modeling approach. The temperature-dependent concentrations and electron occupation ratios of crucial defects of divacancies (V₂) and tri-vacancies (V₃) were given for dynamic and post-irradiation annealing. Besides the common direct dissociation, we found a new approach to eliminating V₂ and V₃ by their recombination with interstitials dissociated from interstitial-relative defects at relatively low temperatures. To effectively eliminate V₂ and V₃ by post-irradiation annealing, we further determined the activation energies of 1.98eV and 1.71eV for V₂ and V₃, respectively. We also found that, within the operation temperature range of devices, the higher the temperature, the better the radiation resistance. It is thus recommended that the optimal temperature of post-irradiation annealing for device performance recovery is near 600K.

The electromechanical properties of nichrome (Ni–Cr 80/20 wt.%) used as a common material for application in thin film strain gauges have been studied. The surface topography and chemical composition of Ni–Cr thin films grown on the glass substrate by magnetron sputtering have been analyzed by atomic force microscope (AFM) and energy dispersive spectroscopy (EDS), respectively. The temperature coefficient of resistance (TCR) has been determined by a Nano-volt/Micro ohm meter. The gauge factor (FG) has been determined by the cantilever method. Low stable TCR values (22 ppm to 46 ppm in the 50–150°C temperature range) have been obtained. Resistance stability is achieved by rapid thermal annealing (RTA) at 300°C for 10 min combined with a 24 h thermal annealing (TA) at 150°C. The desired 45 Ω/m sheet resistance and a gauge factor of 2.6 have been attained for 40-nm-thickness films. The films have very small roughness of 2.1~4.4 nm.

We have prepared the sputtered Ni/n-GaAs Schottky diodes which consist of as-deposited, and diodes annealed at 200 and 400°C for 2 min. The effect of thermal annealing on the temperature-dependent current–voltage (I–V) characteristics of the diodes has been experimentally investigated. Their I–V characteristics have been measured in the temperature range of 60–320 K with steps of 20 K. It has been seen that the barrier height (BH) slightly increased from 0.84 (as-deposited sample) to 0.88 eV at 300 K when the contact has been annealed at 400°C. The SBH increased whereas the ideality factor decreased with increasing annealing temperature for each sample temperature. The I–V measurements showed a dependence of ideality factor n and BH on the measuring temperature that cannot be explained by the classical thermionic emission theory. The experimental data are consistent with the presence of an inhomogeneity of the SBHs. Therefore, the temperature dependent I–V characteristics of the diodes have been discussed in terms of the multi-Gaussian distribution model. The experimental data good have agree with the fitting curves over whole measurement temperature range indicating that the SBH inhomogeneity of our as-deposited and annealed Ni/n-GaAs SBDs can be well-described by a double-Gaussian distribution. The slope of the nT versus T plot for the samples has approached to unity with increasing annealing temperature and becomes parallel to that of the ideal Schottky contact behavior for the 400°C annealed diode. Thus, it has been concluded that the thermal annealing process translates the metal-semiconductor contacts into thermally stable Schottky contacts.

The ordered ferromagnetic–antiferromagnetic ${\mathrm{\text{Ni}}}_{(1-x)}{\mathrm{\text{Mn}}}_x$ alloy nanowires were fabricated successfully by alternating current (AC) electrodeposition into nanoporous anodized aluminum oxide (AAO). The NiMn alloy nanowires were deposited in a simple sulfate bath. Effect of bath composition on Mn content of electrodeposited nanowires as well as the thermal annealing effect on magnetic properties were explored. The magnetic properties of NiMn alloy nanowires were enhanced significantly, compared to corresponding bulk materials. Magnetic parameters, such as coercivity and saturation magnetization were decreased with increasing the Mn content. For thermal annealing process, it was found that these parameters were enhanced with increasing the temperature up to 300${}^{\circ }$C, on the other hand, they were decreased with increasing the temperature to 500${}^{\circ }$C. Moreover, the X-ray diffraction (XRD) patterns revealed that the FCC crystalline structure of Ni turns to an amorphous phase by increasing the Mn content in the nanowires, resulting in a significant reduction in the $H_c$.

The Co/anodic oxide layer/n-GaAs MOS structures have been fabricated by us. The MOS structures have shown an excellent rectifying behavior before and after thermal annealing of 500${}^{\circ }$C for 2 min. It has been stated in the literature that the thermal annealing at a relatively low-temperature can improve the quality and performance of the anodic MOS structure. The current–voltage (I–V) measurements of the annealed MOS structure have been attempted in the measurement temperature range 60–320 K with the steps of 20 K. The I–V plot at 300 K has given the diode parameter values as barrier height ${\mathrm{\Phi }}_{b0}$ = 0.96 eV and ideality factor n = 1.22, diode series resistance R${}_s$ = 124 $\mathrm{\Omega }$ for the annealed sample, and ${\mathrm{\Phi }}_{b0}$ = 0.87 eV and n = 2.11, R${}_s$ = 204 $\mathrm{\Omega }$ for the nonannealed structure. A mean tunneling potential barrier value of 0.59 eV for the anodic oxide layer at the Co/n-GaAs interface has been calculated from the current–voltage–temperature curves. Furthermore, ${\mathrm{\Phi }}_{b0}$(T) versus (2kT)${}^{-1}$ curve has followed a double Gaussian distribution (GD) of the barrier heights. It has been stated that the double GD may be originated from the presence of the surface patches and phases arisen at the anodic oxide layer/n-GaAs interface.

ZrO₂ thin films are deposited by the sol–gel dip-coating technique where the thermal annealing temperature and the number of deposited layers determine the properties of this material concerning the application in field-effect transistor (FET) devices in conjunction with SnO₂ layer, also produced by sol–gel dip-coating. The best annealing temperature for the ZrO₂ film was found as 400°C, along with a small number of layers and the position of the layer inside the oven, which determines the dominant heat transport mechanism of conduction or convection phenomena. The electrical insulating property of ZrO₂ layers was confirmed with the current in the order of pA, even for layers about 100 nm thick. The temperature of 400°C also leads to a lower leak current through the gate in the device, which is three orders of magnitude lower than the source-drain current (in the order of a tenth of $\mu$A).

Potassium tantalite (KTaO${}_3)$ has shown an excellent performance in optoelectronic applications, proving its advantages with respect to fabricating single crystal thin films by ion implantation. This work introduces the damage formation of KTaO₃ under 200 keV He ion implantation at room temperature and He bubbles accumulation. Ion implantation-induced lattice damage before and after annealing was quantitatively analyzed by using the Rutherford backscattering spectrometry in channeling technique. The crystals phase analysis of the samples under different fluences was studied by using the X-ray diffraction technique. For 200 keV He ions, the accumulation and migration of He bubbles were induced by the thermal annealing effect under high fluences of He${}^{+}$. The He bubbles appear obviously coarsening and embrittlement with thermal annealing. The blistering phenomenon caused by He ion implantation is the physical basis for the smart-cut technique, which allows the preparation of high-quality single-crystal films.

Graphene is a two-dimensional monolayer planar sheet containing carbon atoms that are sp²-bonded to one other and tightly packed in a honeycomb crystal structure. Because of its extraordinary qualities, graphene and its derivatives, such as functionalized graphene, graphene oxide (GO), and reduced graphene oxide (rGO), have attracted substantial attention in a variety of applications. The synthesis of graphene and its derivatives of high quality can be accomplished by the employment of a several different methods. When subjected to various reduction methods, GO and rGO emerge with distinctive sets of properties. These features, in turn, have an impact on the graphene’s overall usefulness and performance. This paper provides an overview of the influence that thermal annealing has on the structural and physical properties of graphene. Following the thermal annealing, GO was converted into rGO, and this allowed for the coherent crystal structure of rGO to be restored. It has been found that the annealing temperature has a direct relationship with the crystallite size. The results of the recorded Raman spectra demonstrate that the degree of imperfection ($I_D∕I_G$ ratio) can sometimes be found to increase while at other times it can be found to decrease. There has not been any conclusive evidence to support either the hypothesis that annealing is employed to polish graphene or the hypothesis that this can lead to changes in doping, defect levels, and strain consequences. Additionally, the impact that thermal annealing has on the functionality and performance variations of rGO has been analyzed and explained. This study concluded with a concise review, a discussion of the challenges faced, and a discussion of the opportunities presented by the graphene.

Annealing at high temperatures holds the possibility of concentrating defects in the graphene. Moreover, a significant increase in annealing temperature destroys the surface properties. In this work, the reduced graphene oxide (RGO) was prepared by an electrochemical technique with a high voltage ($V=\sim 24$V, $I=\sim 3.25$A). Then, the potential effects of impact on thermal treatment in a temperature range of 800–1000^∘C in nitrogen-rich environment on the microstructure and surface morphology, thermal stability, phase and crystallinity, structural disorder, absorption properties, and optical properties of RGO for optoelectronic applications were investigated. In addition, a link was established between the estimated crystallite sizes determined by X-ray diffraction (XRD) and Raman data. The microstructural data indicate that the annealing temperature has a significant effect on the microstructure and carbon–oxygen (C/O) ratio. The C/O ratio increases as a function of annealing temperature. Atomic force microscope (AFM) analysis revealed that the root mean square (RMS) roughness of annealed RGO increases with increasing annealing temperature indicating an increase in crystallite size during annealing. Since most organic compounds were removed from the surface of the annealed RGO, oxygen functionalities appear to have minimal effect on the thermal stability of RGO. The size of graphene crystallites increases with annealing temperature, as shown by XRD observations. The crystalline structure was restored by annealing. The Raman results show that in the “low” defect density zone, the $I_D∕I_G$ values increase because a larger defect density causes a stronger elastic scattering. UV–Vis spectroscopy shows that the absorption of RGO is not affected by annealing temperatures between 800^∘C and 900^∘C. The optical bandgap of annealed RGOs decreases from 4.08 to 3.72eV upon annealing in the temperature range of 800–1000^∘C.

Thin films of thulium- and samarium-doped AlN are deposited on silicon (111) substrates at 77 K by RF magnetron sputtering method. 200–400 nm thick films are grown at 100–200 watts RF power and 5–8 mTorr nitrogen, using a metal target of Al with Tm and Sm separately. X-rays diffraction results show that films are amorphous. Cathodoluminescence studies are performed at room temperature and two dominant peaks are observed in Tm at 467 nm from ¹D₂ → ³F₄ transition and 480 nm from ¹G₄ to the ground state ³H₆ transition. Other peaks in the visible region are obtained at 650 nm and 685 nm due to ¹G₄ → ³F₄ and ¹D₂ → ³H₄ transitions. Peaks in the ultraviolet and infrared region are also obtained at 371 nm and 802 nm as a result from ¹D₂ → ³H₆ and ³H₄ → ³H₆ transition, respectively. Sm gives four peaks at 564 nm, 600 nm, 648 nm and 707 nm as a result of ⁴G_5/2 → ⁶H_5/2, ⁴G_5/2 → ⁶H_7/2, ⁴G_5/2 → ⁶H_9/2 and ⁴G_5/2 → ⁶H_11/2 transitions. Films are thermally annealed at 1200 K for half an hour in a nitrogen atmosphere. Thermal annealing enhances the intensity of luminescence.

The Schottky barrier type Ni/$n$-GaAs contacts fabricated by us were thermally annealed at 600${}^{\circ }$C and 700${}^{\circ }$C for 1min. The apparent barrier height ${\mathrm{\Phi }}_{\mathrm{\text{ap}}}$ and ideality factor of the diodes were calculated from the forward bias current–voltage characteristic in 60–320K range. The ${\mathrm{\Phi }}_{\mathrm{\text{ap}}}$ values for the nonannealed and 600${}^{\circ }$C and 700${}^{\circ }$C annealed diodes were obtained as 0.80, 0.81 and 0.67eV at 300K, respectively. Thus, it has been concluded that the reduced barrier due to the thermal annealing at 700${}^{\circ }$C promises some device applications. The current preferentially flows through the lowest barrier height (BH) with the temperature due to the BH inhomogeneities. Therefore, it was seen that the ${\mathrm{\Phi }}_{\mathrm{\text{ap}}}$ versus ${(2kT)}^{-1}$ plots for the nonannealed and annealed diodes showed the linear behavior according to Gaussian distributions.

Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.