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Sampling a signal at elevated sampling rates can be easily achieved by using time-interleaved analog-to-digital converters (TIADCs). TIADCs have more than one ADC in parallel. Each ADC samples the signal with a time gap of one sampling period and hence known as TIADC. The samples from all these ADCs are combined to reconstruct the signal. But the disadvantage of TIADCs is that they have mismatches like sampling time, gain and phase offset. The proposed work focuses on estimation and correction of these mismatches. For estimation of mismatches, teacher learner-based optimization (TLBO) algorithm was used and the estimated mismatches were used for correction by applying suitable operations. The proposed algorithm was applied for four-channel TIADCs. For estimation, a pilot signal is used which in this case is a monotonic sinusoidal signal. The estimation of mismatches was accurate and the correction was implemented for TIADCs with a sinusoidal input signal and the enhancement in signal quality was evaluated by finding signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). There is a significant enhancement in SNR and SNDR. The average enhancements in SNR and SNDR are 50 and 46dB, respectively.

Time interleaving has become a very common choice for increasing ADC speed. However, it is accompanied by defects such as offset, gain and time offset between the individual sub-ADCs, which can seriously degrade the performance of the overall ADC. For the elimination of gain and offset errors, the solution is relatively simple, and the calibration of the time offset is still in the exploratory stage. This paper systematically reviews several current mainstream time-interleaved ADC timing offset correction methods. At the same time, the characteristics and development trend of calibration methods are summarized.