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This paper presented a multiplier-less memcapacitor emulator circuit that is implemented without using a memristor mutator. The proposed circuit is a charge-controlled memcapacitor built with analog blocks. Comparatively, this circuit uses fewer active–passive elements, where all passive elements are grounded. In addition, the most advantageous feature is its tuning which can be done externally by electronic means. Also, the proposed circuit layout has been drawn with minimum metal routing, optimum floor planning, and DRC and LVS checks. The circuit behavior is justified through various simulations in the Cadence Virtuoso-Spectre tool with 180-nm CMOS parameters, and the operating frequency of the proposed circuit is up to 4KHz. In addition, theoretical and simulated results are proven through experimental verification using off-the-shelf IC.

In this paper, we introduce an implementation of a CCII-based grounded inductance operating in class AB. In order to get tunable characteristics of the design, a translinear CCII configuration is used as a basic block for its high level of controllability. A frequency characterization of the translinear CCII is done. In order to optimize its static and dynamic characteristics, an algorithmic driven methodology is developed ending to the optimal transistor geometries. The optimized CCII has a current bandwidth of 1.28 GHz and a voltage bandwidth of 5.48 GHz. It is applied in the simulated inductance design. We first consider the conventional topology of the grounded inductance based on the generalized impedance converter principle. Making use of the controllable series parasitic resistance at port X in translinear CCII, we design tunable characteristics of the inductance. The effect of current conveyor's nonidealities has been taken into account. A compensation strategy has been presented. It is based on the insertion of a high active CCII-based negative resistance and a very low passive resistance. The compensation strategy does not affect the inductance tuning process. Simulation results show that the proposed inductance can be tuned in the range [0.025 μH; 15.4 μH]. The simulated inductance has been applied in a fully integrated tunable high frequency band pass filter to illustrate the versatility of the circuit. The filter is electrically tunable by controlling the conveyor's bias current.

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35$\mu$m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided.

In this paper, a new multiple-gated transistor (MGTR) linearization technique is presented. To simultaneously keep linearity and tuning capability of proposed operational transconductance amplifier (OTA), the auxiliary transistors which are employed for $g_{m3}$ cancellation of differential pair (DP) stage are body-driven through a tune-dependent voltage. By this way, the third-order nonlinearity of DP is reduced for a wide range of transconductance values from 5.1 to 35.6$\mu$A/V. The OTA works with 1.2V supply voltage and its power consumption changes between 137.4 and 156$\mu$W at the entire tuning range. For $G_m=17.6$$\mu$A/V ($V_{\mathrm{\text{tune}}}=0.6$V) and for 0.6$Vpp$ input voltage, the simulation results show 6dB reduction in the total harmonic distortion (THD) of proposed OTA when the MGTR linearization technique is used and 15dB reduction when the tune-dependent body driving is also utilized. The proposed OTA is employed in a third-order low-pass Butterworth filter which is tunable from 2 to 18MHz. The in-band IIP3 of filter is 16.9 and 12.4dBm, respectively, for 2 and 18MHz cutoff frequencies while the two-tone input voltage is applied at 1MHz.

Traditional filters usually have low Q and gain values and it is difficult to adjust their center frequencies. Moreover, it is very complicated to analyze their transmission charateristics through conventional methods. Therefore, in this paper, a tunable differential N-path bandpass filter that uses a new adjoint network method to analyze the transmission characteristics of the differential N-path structure is proposed. The filter circuit adopts a novel circuit structure consisting of two differential N-path structures, two transconductance amplifiers and an off-chip transformer. The differential structure eliminates even harmonics, the transconductance amplifier increases the circuit gain and the off-chip transformer acts as a balun, improving the filter’s Q value and achieving impedance matching. Unlike the traditional switching capacitance method used for analyzing the differential circuit structure, the method proposed in this paper does not involve complicated calculus operations. In fact, the method greatly simplifies these complex operations, and the transmission function of the circuit can be obtained through simple algebraic operations. The proposed filter was designed using TSMC 180nm CMOS process. Simulation results for a differential four-path bandpass filter formed under 1.2V supply voltage show that the gain of the filter is greater than 8.5 dB, the center frequency can be adjusted from 0.1GHz to 1GHz, the in-band insertion loss S11 is greater than 10 dB, the out-of-band IIP3 is greater than 10 dBm, the out-of-band rejection is 28 dB and the noise figure is less than 2.2 dB at $f_s=300$MHz.

A gain and bandwidth tunable active-RC multiple-feedback (MFB) fourth-order low-pass filter is presented, which exhibits four different bandwidths of 10, 20, 30 and 40MHz and four different gain settings of 0, 4, 8 and 12dB to meet the requirements of the cellular vehicle-to-everything (C-V2X) standards. The filter uses the cascade of two biquad MFB cells. Gain and bandwidth programmability is achieved by using programmable capacitor and resistor arrays. A logic block is implemented in the filter to adjust the gain transfer function for every tuning option. Also, two-stage miller op-amp topology is chosen to implement biquad MFB cells for minimum complexity and maximum efficiency in low voltage operation. The filter is designed in 65-nm CMOS technology and occupies a 0.181mm² area and it totally consumes 13.41mW from the 1.2V supply voltage. To the best of the author’s knowledge, this work is the first CMOS baseband filter design that includes both gain and bandwidth programmability implemented for C-V2X applications.