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This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration.

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405MHz medical implant communications service (MICS) band applications using 0.18-$\mu$m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5dB conversion gain, 1.85dB noise figure, and IIP3 of $-30$dBm while consuming 440$\mu$W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29mm².