Narrow Results

In this paper the design and simulation of an all-optical three-input exclusive-OR (XOR) gate based on semiconductor optical amplifier-Mach–Zehnder interferometer (SOA-MZI) configuration is presented. This gate is constructed of three semiconductor optical amplifiers placed at the arms of the two coupled Mach–Zehnder interferometers. The outputs of these two MZIs are combined at the output port to form the final signal. The proposed scheme does not need a continuous wave (CW) laser for its operation and is designed so that the minimum number SOAs are employed. Theoretical analyses and simulations show that this structure acts as an all-optical three-input XOR logic gate which has many applications in optical data communications.

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

In modern communications, code converters and accurate data transmission are essential. This paper presents a new code converter (i.e., Binary to Gray and Gray to Binary) and Parity Checker using mixed logic design. Mixed modeling will be better to achieve low power, high speed and fewer transistors instead of considering a single logic style for array structures. It is important to note that additional metal layers are required for implementation. The HSPICE simulations have been done on these circuits with various supply voltages and frequencies. The existing circuits are compared with mixed logic design circuits and found that the proposed designs show better performance. Especially when compared with FS_XOR1 (which produces better results than others), the power consumption of Mixed logic design is reduced by 5.40%, the speed is improved by 14.89% and PDP is also decreased by 19.48% in the case of Binary to Gray. Moreover, significant improvements can be seen with other existing designs.

With our lives trundling toward a fully-digital ecosystem in break-neck speed, today’s encryption and cryptography are facing the challenge of ensuring security and future-readiness of our transactions. When such transactions involve multiple hands, transmission of such data in discrete and recoverable parts (secret shares) guarantees confidentiality. This paper’s objective is to present a foolproof way of multiple secret sharing, eliminating issues such as half-toning and degradation of visual quality of the recovered images. This $k$ out of $n$ steganography and authenticated image sharing (SAIS) scheme for multiple color images generates $n$ relevant shares with the ability to reconstruct the secret images using $k$ shares and facility to find out any move for appropriation of share cover images. The key aspects of this proposed scheme is to use simple Boolean and arithmetic operations with reduction of computational complexity from $O(n{log}^{2}n)$ to $O(n)$ and to share multiple images without any pixel expansion.

This study demonstrates the development of an innovative $n$-bit less power ripple carry incrementer (RCI) and decrementer (RCD) circuit, respectively, devised using quantum dot cellular automata (QCA). In order to increment or decrement two numbers, RCI and RCD are essential. With a revised configuration of the AND gate, half adder, and XOR gate circuit, the suggested ripple carry incrementer and decrementer circuits are realized. Modern designs for the XOR and half adder are contrasted with these freshly created ones. Circuits are designed using QCA designer 2.0.3. The 4-bit RCI, 8-bit RCI, and 16-bit RCI as well as 4-bit RCD, 8-bit RCD, and 16-bit RCD simulation results are compared to the theoretical findings.