International Journal of High Speed Electronics and Systems

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

Circuits with diverse electrical behavior are often placed in close physical proximity in order to achieve high-levels of on-chip integration. The activity of certain types of circuits can generate harmful interference, and degrade the performance of the system through electromagnetic coupling. Considerable effort in system-on-a-chip implementations is in fact related to technology and architectural considerations for minimizing this interference. This is especially the case in systems that have exacting requirements on the dynamic range such as those for wireless applications.

In this paper, we will discuss the evolution of techniques for modeling and analyzing these sources of noise generation and interference. We will provide a physical description of the problem. Techniques for extraction of electrical models to represent the media that support these noise sources will be covered. Macromodeling techniques will be discussed. Finally we will introduce the concept of functional modeling of circuit functions and present such a model for an integrated flash analog-to-digital converter.

This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

In this paper, we present a detailed analysis of VCOs using a capacitively degenerated negative resistance cell. The negative resistance cell using capacitive degeneration has a higher maximum attainable oscillation frequency and a smaller equivalent shunt capacitance when compared to the widely used cross-coupled negative-g_m cell. These properties are of particular interest for the design of high-frequency and/or wide tuning range VCOs. The negative resistance provided by a traditional capacitively degenerated negative resistance cell is lower than that provided by a cross-coupled negative-g_m cell. We present an active capacitive degeneration topology that overcomes this limitation. To validate this circuit topology we use two test vehicles. The first test vehicle is a 5.3 GHz VCO designed in a 0.25 μm CMOS technology and the second test vehicle is a 20 GHz VCO designed in a 0.25 μm BiCMOS technology. Measurement and simulation results from both test vehicles effectively demonstrate the efficacy of the capacitive degeneration technique.

Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial, the general implementation issues and recent developments of frequency synthesizer design are discussed. Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.

Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os. This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.