International Journal of High Speed Electronics and Systems

We present design considerations for high speed high swing differential modulator drivers in SiGeBiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.

We review the main results obtained with our recently introduced passively fundamental mode-locked Er:Yb:glass lasers mainly in the context of telecom applications, and we discuss their key enablers. Specifically, we focus on the aspects of the lasers for application in the time-domain for optical time-division multiplexing and in the wavelength domain for dense wavelength-division-multiplexing.

Inter symbol interference (ISI) caused by dispersion in optical fibers is the major limiting factor on the achievable data rate or transmission distance in high-speed fiber-optic interconnects¹. Compared with optical-domain and other electrical-domain dispersion compensation methods, duobinary coding technology is used due to its higher spectral efficiency. In this paper, a monolithically integrated duobinary optical transmitter has be designed and fabricated in standard 0.18 μm CMOS technology. This transmitter consists of a duobinary encoder and a VCSEL driver. The master-slave D flip-flop structure is used to generate the wideband one bit delay which is important for the realization of duobinary signal. An open drain structure is used in VCSEL driver design to provide the higher current output in low supply voltage condition. This duobinary transmitter can operate up to 5 Gb/s with 20 mA current output. The current consumption is only 50 mA under 1.8 V supply voltage.

A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGeBiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.

An analysis of first-order polarization-mode dispersion (PMD) effects in a 40-Gb/s optical system is used to compare different electronic equalizer architectures as potential PMD compensators. Both linear and nonlinear equalizers are considered employing symbol-spaced and fractionally-spaced taps. It is found that a decision feedback equalizer consisting of a 3-tap symbol-spaced feedforward equalizer and a 1-tap feedback equalizer effectively eliminates PMD as the dominant length-limiting factor in most 40-Gb/s optical systems. Such an equalizer would entail less complexity than several previously reported electronic PMD compensators.

Serial IOs are widely used to expand the system bandwidth in communication systems. This paper provides an overview of serial IO design trade-offs with regard to power, cost, and performance. Circuit techniques are discussed to achieve low jitter and high bandwidth.

This paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

This paper describes our InP-based heterojunction bipolar transistor (HBT) technologies and circuit design techniques for small-scale-integration (SSI) and medium-scale-integration (MSI) circuits for 40- to 100-Gbit/s-class optical communications systems. The circuits include a sub-4-ps emitter-coupled logic (ECL) gate, 100-Gbit/s selector circuit, 90-Gbit/s decision circuit, 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs, aver-40-Gbit/s 16:1 MUX IC, and 40-Gbit/s full-clock-rate DEMUX with a clock and data recovery (CDR) circuit. This paper demonstrates that InP-based HBT technologies and our circuit design techniques are attractive for fabricating ultrahigh-speed SSI circuits with data rates approaching 100 Gbit/s and low-power MSI circuits with data rates of over 40 Gbit/s.

A time-division-multiplexing (TDM) system transceiver with 4–channel 10 Gb/s interfaces to achieve 40 Gb/s non-return to zero (NRZ) transmission is presented. The front-end components are implemented in an indium phosphide double hetero-junction bipolar transistor (InP DHBT) technology. They include a 4:1 multiplexer with a voltage controlled oscillator and clock multiplication unit, modulator drivers for electro-absorption and differential lithium-niobate modulators, trans-impedance amplifier, limiting amplifier and 1:4 demultiplexer with clock and data recovery circuit. The transceiver was used to teat optical transmission over a 2.26 km link with a 40 Gb/s, 2³¹-1 pseudo-random bit sequence (PRBS) data. The transmitter achieves better than 12.9 dB extinction ratio, 1 ps added root mean square (RMS) jitter and 4 dBm output power. Without any optical amplification the receiver achieves -9.1 dBm back to back sensitivity at a bit error rate (BER) of 10^-12 and a high dynamic range of 12.5 dBm.

This paper describes Inter-frame Ling Signaling (ILS) protocol technology and its implementation in a 10-Gigabit Ethernet (10GbE) physical layer (PHY) LSI and optical transceiver module. The ILS can realize SDH/SONET-compatible operations, administration, maintenance, and provisioning (OAM&P) functions for PHY of 10GbE networks by inserting OAM&P information in the inter-frame gap periods. The coding features include 10GbE PHY upper compatibility, error detection capability, and disparity neutral characteristics. The 10GbE PHY LSI with the ILS function was fabricated using 0.18-um SOI CMOS technology to achieve high-speed and low-power performance. The main features of the high-speed circuit design are an inductive-load buffer, high-speed clock and data recovery (CDR), and pre-emphasis/equalizer circuits. The LSI function meets IEEE 802.3ae specifications with the very low-power consumption of about 1.2W. An XENPAK transceiver with ILS function using the LSI was also fabricated to make it easy to implement the ILS function in optical transport network systems such as WDM, OADM, OXC systems and L2/L3 switches. The key features of the module include a 1.3-um DFB laser module with highly reliable transmission performance and a small EML driver integrated module. ILS protocol operation is verified by experiment with XENPAK modules emulating the optical transport system.