Brainware: Bio-Inspired Architecture and Its Hardware Implementation

The following sections are included:

• Series Editor's Preface

• Volume Editor's Preface

• Contents

A multiple-input transistor has been developed by a simple modification in the regular MOSFET structure. The transistor turns on when the weighted sum of input signals exceeds the threshold voltage of the device. Due to its functional similarity to McCulloch and Pitts Model of a neuron [1], it is named neuron MOS transistor or vMOS (neuMOS) for short. Such a functionality enhancement in the elementary device has shown a great impact on the way of constructing circuits and systems. In applications to binary logic circuits, the number of transistors and interconnects has been remarkably reduced. The concept of soft hardware, i.e., the real-time reconfigurable logic gates has been also developed using vMOS. Several hardware-computing schemes have been developed in which algorithms are directly carried out in the circuits using vMOS' as key elements. This allows real-time response of a system in real-world data processing. In order to implement intelligent systems on silicon, the association processor architecture has been developed based on a psychological brain model and implemented in the vMOS hardware-computing scheme. Applications of the association processor architecture to recognition problems as well as to practical problems are presented.

An adaptive-leaning neuron circuit composed of MFSFET and complementary unijunction transistor (CUJT) oscillation circuit was fabricated on an SOI (silicon-on-insulator) structure as the first step to the next-generation neural network. SrBi₂Ta₂O₉ (SBT) was selected as a ferroelectric gate material and patterned by a newly developed selective etchant, NH₄F:HCl. It was demonstrated that the fabricated MFSFET showed good memory operations and gradual learning effect in which the drain current was changed gradually by applying a number of input pulses with a sufficiently short duration time. It was also demonstrated that the output pulse frequency of neuron circuit increased gradually as the number of input pulses was increased. Finally, the problem of small output pulse height of the neuron circuit was solved by replacing CUJT oscillation circuit with the CMOS Schmitt-trigger circuit.

This chapter presents an analog-digital merged neural circuit architecture using pulse width modulation (PWM) signals. In particular, circuits implementing bipolar-weighted summation and arbitrary nonlinear transformation are described. The weighted summation circuit attains 8-bit precision in SPICE simulation by compensating parasitic capacitance effects. Measurement results of a prototype chip fabricated using a 0.6 µm CMOS process demonstrate that the overall precision is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation. The arbitrary nonlinear nonmonotone transformation is achieved in conversion from analog voltage to PWM signals using plural comparators. Using this technique, we have fabricated a CMOS chaos chip, and have succeeded chaotic signal generations which exhibit bifurcation behaviors closely similar to those predicted by numerical simulation.

Natural vision systems are yet unrivaled with regard to parameters such as performance, size, and power consumption in comparison to todays technical and predominantly digital implementations. This especially holds for complex vision tasks, e.g., in image sequence analysis. Application-specific constraints, imposed by many real time vision tasks, can be met by an opportunistic design of bio-inspired circuits and systems employing analog and mixed-signal design techniques. Consequently, a plethora of vision chips exploiting basic principles have been designed but only few can actually serve in real applications. Today, the modeling of complete application systems requires a hybrid approach and an appropriate design methodology to assure the viability of the resulting integrated system. This paper reports on a research activity that tackles the development of a corresponding design methodology. Several application projects, e.g., OCR, automotive image processing, eye tracking, and visual inspection, will be introduced, that were subject to this design methodology and gave feedback to advance the methodology for systematic design of integrated cognitive systems.

We propose simple analog MOS circuits with a correlation model based on the insect motion detectors aiming at the realization of fundamental motion-sensing systems. The model makes the circuit structure quite simple, compared with conventional velocity sensing circuits. SPICE simulation results indicate that the proposed circuits compute local velocities of the moving light spot and have direction selectivity for the spot, which implies that a high-resolution motion-sensing chip can be realized by current analog VLSI technology.

This chapter proposes a design of cell circuits for implementing cellular-automaton devices that perform morphological picture processing. To produce the morphological processing, we present the idea of using the silicon functional device, νMOS FET. We designed sample cell circuits for several morphological processing (noise cleaning, edge detection, thinning and shrinking in an image). A low dissipation of about 10 µW per νMOS FET threshold logic circuits can be expected at 1 MHz operation; therefore, 10⁵ or more cells that operate in parallel can be integrated into an LSI.

As the novel types of chaos-generating circuit usable for the bio-inspired information processing with their simple and suitable structure for the integration, capacitor-transistor pair (CTP), return-map unit and CMOS chaos multivibrator (CMV) have been developed. Noise source for the Boltzmann machine utilizing CTP or CMV, and the coupling experiment with the return-map unit are discussed. Operation of the pipelined AD converter as the chaos generating circuit under the map function of the Bernoulli-shift is also demonstrated.

In developing neuromimetic engineering systems, the choice of neuron-like element is critical, because this element determines the functional ability of the system. According to recent neuroscience research, a neuron is expected to perform sophisticated information processing, making use of the complex physiological properties of its dendrites. In this chapter, the computational function of neuronal dendrites is explored based on mathematical models. Theoretical analyses show that a passive dendrite is capable of complex logic operations by means of nonlinear synaptic interactions. Computer simulations show that active dendrites integrate synaptic inputs locally and then hierarchically according to synaptic organization and dendritic geometry. Based on these results, a formal neuron is proposed which simply and sufficiently describes the actual properties of the dendrites. This model is therefore suitable for constructing a large-scale network without the loss of the active dendrites' essential responsiveness. These modeling studies provide novel perspectives on the computation in a single neuron with a complex dendritic tree.

The following sections are included:

• Appendix A Compartmental Model of Pyramidal Neuron

• About the Authors

• Keyword Index