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A Low-Voltage Two-Stage Enhanced Gain Bulk-Driven Floating Gate OTA

https://orcid.org/0000-0002-2051-2711

Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj 211004, Uttar Pradesh, India

E-mail Address: dubey.tanmay@gmail.com

Corresponding author.

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Vijaya Bhadauria

Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj 211004, Uttar Pradesh, India

E-mail Address: vijaya@mnnit.ac.in

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https://doi.org/10.1142/S0218126621502200Cited by:0 (Source: Crossref)

Abstract

This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18- $μ$ m CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42dB. The circuit delivers $-$ 65dB of HD₃ and $-$ 56dB of THD when a 0.2-V_pp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

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