Journal of Circuits, Systems and Computers

A multichannel transceiver design with low hardware complexity, flexibility and efficient spectrum use intended for Impulse Radio (IR) Ultra-Wideband (UWB) apertures, is proposed in this paper. The transceiver supports 14 channels and is implemented in TSMC CMOS process. The transmitter adopts a symmetrical triangular narrow pulse generator, a multiband LC-VCO, a mixer and a Variable-Gain Amplifier. A digital control of transmitter output power and carrier frequency is achieved by a current-steering Digital-to-Analog Converter (CS-DAC). The receiver follows the noncoherent Energy Detection (ED) scheme including Low-Noise Amplifier (LNA) which takes the benefits of the body biasing technique to further reduce power consumption, squarer and comparator. The LNA achieves high gain of up to 30dB allowing to enhance the receiver sensitivity which is $-$83.7dBm at 25Mbps. The transmitter provides output pulses with a width of 3ns, a pulse repetition rate of 20ns and a maximum Power Spectral Density (PSD) of $-$42dBm/MHz. The power consumptions of transmitter and receiver are 35.6pJ/bit and 0.207nJ/bit at 25Mbps, respectively. Maximizing utilization of the scarce wireless spectrum, enhancing spectral flexibility and efficiency and reducing power consumption are the main contributions brought by this work, enabling this transceiver to be able to deal with the current debate on producing single multifunctional Cognitive Radio (CR) UWB systems.

Electrocardiogram (ECG) is a graphical visualization of the electrical activity of the human heart that is recorded by placing a surface electrode at standardized position on a person’s chest. ECG signals suffer from artifacts/noises due to baseline wander (BW), electrode artifacts, muscle artifacts, power-line interference and channel noises during acquisition and transmission of the ECG signals. Reduction of these artifacts is crucial for efficient diagnosis and interpretation of the human heart condition. In this paper, an effective adaptive noise canceller (ANC) based on empirical mode decomposition (EMD)-Jaya algorithm is proposed for denoising electrocardiogram. In this approach, intrinsic mode functions (IMFs) produced by EMD are used as reference and Jaya algorithm is used to calculate optimum weights of finite impulse response (FIR) filter. This scheme is compared with EMD, wavelet transform (WT) thresholding, and hybrid EMD-least mean square (LMS) approaches through extensive simulation on noise corrupted ECG besides verifying the robustness with real ECG signals. The performance of the proposed technique is assessed using standard metric signal-to-noise ratio (SNR) with different contamination levels. The results obtained demonstrate the superiority of the hybrid when compared to other competing approaches.

In order to protect audio files, we propose in this paper a new integration scheme for blind audio file watermarking. The goal is to find a compromise between capacity and imperceptibility in order to hide as much data as possible while minimizing file degradation. This integration scheme is implemented in the three insertion domains: spatial, frequency and multi-resolution domains. For the spatial-domain integration, the mark is inserted directly into the data samples. For the frequency-domain integration, a Discrete Cosine Transform is applied to the audio frames; after the thresholding and quantification step, the watermark is inserted into the Discrete Cosine Transform coefficients to obtain the watermarked file. For the multi-resolution-domain insertion, a single-level Discrete Wavelet Transform is applied using the scaling low-pass filter and wavelet high-pass filter. The watermark integration is then performed using the obtained AC coefficients. The proposed concealment process combines three values to integrate two bits and only one may be modified, which reduces the probability of change unlike other approaches. This implies less modification and therefore less distortion of the host file; this explains the good Signal-to-Noise Ratio obtained of more than 59dB for the spatial-domain integration and therefore a reasonable imperceptibility. An evaluation of the watermark’s robustness demonstrates that the proposed schemes generate reasonably robust watermarked samples against various attacks with a high-quality watermark with normalized cross-correlation greater than 0.9 for the three insertion domains.

In this work, a three-input single-output structure of current-mode second-order multifunction filter is presented. Two multiple-output second-generation current conveyors serve as the active building blocks. Additionally, two grounded resistors and two grounded capacitors are employed as passive components. On appropriate selection of the input values, all second-order filter functionalities, namely, low-pass, high-pass, all-pass, band-pass and band-reject, can be availed. Proposed filter shows good sensitivity performance and supports high frequency operation. Non-ideal analysis is presented to show the intactness of filter characteristics under runtime conditions. Simulation results show good correlation with the theoretical performance of the proposed filter.

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included.

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32nm CNTFET model.

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35$\mu$m CMOS AMS process technology with $3.3$V supply voltage and an input common-mode range of $1.15–2.15$V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of $32.32$mV with $2.49$mV 3$\sigma$ deviation, a slew rate of $8.29$V/ns with $0.45$V/ns 3$\sigma$ deviation, and a propagation delay of $4.16$ns with $0.15$ns 3$\sigma$ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of $63.01^{\circ }$, and a high-gain of $79.22$dB with $1.92^{\circ }$ and $4.86$dB 3$\sigma$, respectively, by using $1\text{pF}$ load capacitance.

Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in nanocircuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a new $5\times 5$ reversible block and then its quantum realization is given using the Miller et al. method. In the following, an effective reversible design of D flip-flop is introduced using the proposed reversible block. Finally, four types of reversible shift register including serial-in to parallel-out (SIPO), parallel-in to parallel-out (PIPO), parallel-in to serial-out (PISO) and shift counter are proposed using the proposed reversible flip-flop. The evaluation results show that the proposed circuits are superior compared to the existing designs in terms of quantum cost (QC).

In this paper, a new true random number generator (TRNG) based on a new variable differential ring oscillator has been presented. In this structure, the ring oscillator’s jitter is considered a random phenomenon. The jitter of the proposed ring oscillator is driven by thermal noise and flicker noise so that the generated jitter is random. In this paper, a new variable differential ring oscillator has been designed. The stage of this ring oscillator is changed randomly in order to create random jitter. A new differential delay cell has been proposed to boost the speed of TRNG and random jitter. The proposed random number generator (RNG) is robust against temperature variations of $-$40–120${}^{\circ }C$ and voltage variations from 0.8 to 1.8V. The proposed system’s bitrate is 50MB/s and its efficiency is 30.03Mb/mJ. This process has been implemented in the 0.18um CMOS process. Simulation results have been presented in Hspice software and cadence. The output bit images have been displayed by Matlab software.

This paper presents a new switched-ladder structure for multilevel converter which consists of several bidirectional and unidirectional switches along with DC voltage sources. The values of DC sources in the proposed topology are determined based on a new mathematical algorithm. The proposed multilevel converter is an extended structure, which can produce any levels at output voltage waveform. To prove the merits of the proposed structure, the proposed converter is compared with other similar structures. According to comparison results, it is shown that the presented structure requires the least numbers of DC sources, IGBTs, drivers and on-state switches. Also, the value of voltage rating of the switches is analyzed. The experimental results are provided for the proposed 17-level converter to prove the performance of suggested structure.

A new voltage mode Proportional-Integral-Derivative (PID) controller employing Current Differencing Buffered Amplifier (CDBA) is presented. The proposed PID controller employs a canonical number of capacitors without requiring any passive components matching conditions. The element values are expressed in terms of PID parameters. Workability of the proposed controller is demonstrated through SPICE simulations for which CDBA is realized using Current Feedback Amplifier (CFA). The simulation results are found in close agreement with the theoretical results.

This paper presents six different meminductor emulator circuits based on operational amplifiers. Five circuits of meminductor emulators have been proposed using two operational amplifiers, one memristor, three resistors and one capacitor, whereas the sixth circuit uses two operational amplifiers, two memristors, one resistor and two capacitors. All circuits of the proposed meminductor emulators are very simple over most of the realizations of meminductor emulators in the literature. The behaviors of meminductor emulators are satisfactory over a wide range of frequencies. The proposed configurations of meminductor emulators have been simulated by the LTspice tool. The SPICE models of both operational amplifier (AD711) and memristor have been used for simulation. The workability of the proposed meminductor emulators has also been verified using the basic and well-known structure of operational amplifier. In addition, the pinched hysteresis loop obtained by the simulation results of meminductor emulator has been achieved by the experimental results as well. Chaotic oscillator has been designed using the proposed meminductor emulator to prove the worthiness of the design.

This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18-$\mu$m CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42dB. The circuit delivers $-$65dB of HD₃ and $-$56dB of THD when a 0.2-V_pp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper.

We introduce a clear constructive methodology of approximation and synthesis of analog functions using the transfer characteristics of the basic differential pair. The new methodology provides circuit designers with an easy-to-understand solution of the function approximation problem employing MOSFETs in weak inversion. It further provides compact formulas for the optimal coefficients involved in the approximation. We confirm the design methodology using SPICE through two examples involving the exponential function.

In this paper, two simple circuits are presented to emulate both memcapacitor and meminductor circuit elements. The emulation of these components has crucial importance since obtaining these high-order elements from markets is difficult when compared to resistor, capacitor and inductor. For this reason, we proposed Multi-Output Operational Transconductance Amplifier (MO-OTA)-based electronically controllable memcapacitor and meminductor circuits. To operate the MOS transistor as a capacitor, drain and source terminals are connected to each other. The memcapacitor behavior is obtained by driving the connected terminals with suitable voltage values. Only a few active and grounded passive components which are found in markets easily are used to emulate meminductive behavior. Furthermore, all passive elements in the circuit are grounded. All simulation results for memcapacitor and meminductor emulators are obtained successfully when compared to previous studies. For all analyses, MO-OTA is laid using the Cadence Spectre Analog Environment with TSMC 0.18$\mu$m process parameters and occupied a layout area of only 86.21$\mu \mathrm{\text{m}}\times 34.67\mu$m.

VLSI technology makes the integration of multiple electronic components into a single electronic chip possible but Moore has already predicted that further miniaturization of VLSI chips will cause excess heat dissipation. Because of this impediment faced by this technology, the scientists have turned their focus to nano-technological alternatives to keep up the continuous device improvement and continue with the miniaturization procedure without facing any hurdle from the aspect of heat dissipation and space and time complexity. Memristor can be such a nano-alternative, which has the potential of very rapid execution, miniaturization and very low power consumption compared to transistor-based technology. The main objective of this paper is to show an application of symmetric function in cryptography. In order to do so, first, three-input and five-input symmetric functions are implemented in memristor-based nanocrossbar circuits. Then a dynamic circuit of symmetric functions is implemented where the input voltages convert the circuit to three-input or five-input symmetric function circuit as and when required. The simulation results show the satisfactory behavior of our proposed design.

The work reports two different configurations to emulate the floating memristor and inverse memristor behavior. The presented circuits are based on a modified concept of active element VDTA (Voltage Differencing Transconductance Amplifier) termed as MVDTA. The reported floating memristor employs only a single MVDTA and single grounded capacitance. On the other end, the floating emulation circuit of inverse memristor emulator is based on two MVDTAs and single grounded capacitance. The behavior of the realized element for both the configurations can be tuned electronically through biasing voltage. Also, there is no employment of any commercial IC or external circuitry for multiplication of analogue voltages which is generally required to implement memristive elements. Along with the circuit implementations, mathematical properties of ideal memristor and inverse memristor considering both symmetric as well as nonsymmetric models are discussed. All the emulation circuits are verified by executing simulations using CMOS 0.18um process technique under PSPICE environment. The reported circuits are also realized using commercially available IC LM13700 and results are presented.

This paper introduces a novel current tunable biquad universal filter structure based on four Z-copy current conveyor transconductance amplifiers (ZC-CCTAs) and two capacitors. The proposed structure is a mixed mode topology that allows current and/or voltage signals at input and output terminals and can generate various biquad filtering responses namely all pass (APF), band pass (BPF), band reject (BRF), high pass (HPF) and low pass (LPF) in each of the four possible modes as current input current output (CICO), current input voltage output (CIVO), voltage input voltage output (VIVO) and voltage input current output (VICO) form. The proposed topology is resistor free and posses electronic tuning capability of filter characteristics by adjusting bias current(s) of the device. Besides, the proposed topology also offers reasonable total harmonic distortion (THD) up to 2.18% and leads to less sensitivity with respect to active-passive components. The simulation and design of the circuit is performed using 0.18-$\mu$m CMOS technology environment in PSPICE.

An ultra-wide bandwidth fully differential two-stage 65nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103MHz 3-dB bandwidth with a 2pF load capacitor. It consumes 9mA current from 1.2-V supply. Transition frequency of 2.4GHz and a gain of 29dB is accomplished. A 2pF load capacitance can be driven at a phase margin of $55^{\circ }$. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40$\mu \mathrm{\text{m}}\times 60\mu$m layout area and ultra-wide 3-dB bandwidth.

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312mV with a temperature coefficient (TC) of 38.85ppm/^∘C over a wide temperature range of $-40^{\circ }$C to 125^∘C with a supply voltage of 0.8V. The line sensitivity is 0.027% $∕\mathrm{\text{V}}$ with a supply voltage ranging from 0.8V to 3V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as $-80.84$ and $-71.66$dB at 100Hz and 100kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027mm².