Journal of Circuits, Systems and Computers

For the problem of target recognition of synthetic aperture radar (SAR) images, a method based on the combination of bidimensional empirical mode decomposition (BEMD) and extreme learning machine (ELM) is proposed. BEMD performs feature extraction for SAR images, producing multi-layer bidimensional intrinsic mode functions (BIMF). These BIMFs covey the discrimination of the original target while effectively eliminating the noises. ELM conducts the classification of each BIMF with high efficiency and robustness. Finally, the decisions from different BIMFs are fused using a linear weighting strategy to reach a reliable decision on the target label. The proposed method compensates the relatively low adaptivity of ELM to noise corruption by BEMD feature extraction. Moreover, the multi-layer BIMFs provide more discriminative information for correct decision. Hence, the overall recognition performance can be improved. As an efficient recognition algorithm, the proposed method can be used in an embedded system for wide applications. Experiments are designed and implemented on the moving and stationary target acquisition and recognition (MSTAR) dataset. The proposed method is tested under both the standard operating condition (SOC) and extended operating conditions (EOCs). The results reflect its effectiveness and robustness via quantitative comparisons.

The transportation sector uses a big portion of the world’s petroleum products thus increasing the greenhouse gas (GHG) emissions. Electric vehicles (EVs) have the potential to solve GHG emissions. The requirements for EVs have brought many different problems such as the conversion of voltage level from the battery to other parts of the EV using DC–DC converters. The design and implementation of a nonisolated DC–DC buck converter with single input and dual output are presented, which is also called the single-input multiple-output (SIMO) converter. The converter is designed especially for electric cars. The battery (48V) of the electric vehicle is used as an input to the SIMO. Small-signal analysis and effective control strategy for the converter are presented in this paper. The simulation of the system is performed and compared with the experimental results.

With the rapid development of Artificial Intelligence (AI), the problem of AI security has gradually emerged. Most existing machine learning algorithms may be attacked by adversarial examples. An adversarial example is a slightly modified input sample that can lead to a false result of machine learning algorithms. This poses a potential security threat for many AI applications. Especially in the domain of robot path planning, the adversarial maps may result in multiple harmful effects on the predicted path. However, there is no suitable approach to automatically identify them. To our knowledge, all previous works used manual observation method to identify the attack results of adversarial maps, which is time-consuming. Aiming at the existing problems, this paper explores a method to automatically identify the adversarial examples in Value Iteration Networks (VIN), which has a strong generalization ability. We analyze the possible scenarios caused by the adversarial maps. We propose a training-based identification approach to VIN adversarial examples by combining the path feature comparison and path image classification. Experiments show that our method can achieve a high-accuracy and effective identification on VIN adversarial examples.

With the popularization of computers and the development of information engineering, the emergence of search engines makes it possible to get the information needed from big data quickly and efficiently. However, in recent years, a multiplicity of new viruses have been propagated by search engines. Many researchers choose to cut off the source of virus propagation, ignoring the virus immunization strategy based on the search engine. In this paper, we analyze the impact of search engines on virus propagation. First, considering the immune effect and cost, two kinds of immune mechanisms based on the search engine that have greater practicability are defined. Second, immune mechanisms based on the search engine are theoretically analyzed by the iteration method and the dynamic method. The results show that this immunization strategy can slow down or eliminate the propagation of a virus to a certain extent. Third, three real social network data sets are used to simulate and analyze the immune mechanism. We find that when the proportion of nodes being infected and the proportion of infected nodes being identified by the search engine satisfy a certain relationship, our immune mechanism can inhibit the spread of viruses, which confirms our theoretical analysis results.

In this study, a new sinusoidal fractional oscillator circuit in which the fractional low-pass filter and fractional differentiator form a closed loop has been introduced. The single series $R-C$ pair and Valsa method have been used to imitate the fractional-order capacitor. Two different sinusoidal signals with different phases are available at output ports. An integer version of the proposed oscillator is not possible, only the fractional version is valid, that is a noticeable feature. The introduced circuit has been simulated by employing SPICE software. The proposed fractional oscillator is also verified by implementing circuit with AD817ANs and passive components, experimentally.

The objective of this paper was to propose a second generation voltage conveyor (VCII)-based new voltage mode biquad, equivalent to Kerwin–Huelsman–Newcomb (KHN) biquadratic circuit. The proposed circuit helped to efficiently add and subtract voltages by exploiting the virtual ground at one of the terminals of VCII, and without compromising on the features of the filters, such as the independent tuning of the quality factor (Q) and characteristic frequency (${\omega }_o$). The proposed circuit’s viability has been verified through LTspice simulations. The paper also presented the nonideal, the sensitivity, distortion, linearity and Monte Carlo analysis of the filters of the proposed circuit.

A compact low-cost metamaterial circular monopole antenna for LTE applications is presented here. This paper addresses an asymmetric circular split-ring radiator for 2.6GHz (LTE-7 band), 3.5GHz (LTE-22 band). The design here employs split rings with varying split gaps in the consecutive ring layers of the radiating element which helped in achieving better impedance matching for obtaining multiband operation. The work presented here demonstrates the feasibility of achieving double negative material property, without loading the SRR’s separately in the system. The antenna was modeled using a 1.6mm thick FR-4 lossy material. The simulated results were compared with measured results and found to be in good agreement with each other. Employing asymmetric split ring as radiator helped in achieving 29% of size reduction in the patch layer. The modified split-ring radiator achieved directional radiation pattern and minimum side-lobe levels with a peak gain of 1.29 and 0.204dB at the lower band and upper band, respectively. The compact dimension $45\times 40{\text{mm}}^2$ of the radiating system makes it suitable for LTE-WLAN/Wi-Max applications.

Common spatial pattern (CSP) is a popular algorithm for spatial filtering and subsequent feature extraction in motor imagery-based (MI) brain-computer interface (BCI) systems. The performance of CSP, however, depends heavily on the subject-specific frequency band and time segment used for classifying mental tasks. Accurate selection of most informative frequency band and time segment poses a great challenge. In this study, quantum particle swarm optimization is proposed for sole selection of frequency band and joint selection of frequency band and time segment, which are realized by a wrapping approach, incorporating CSP for feature extraction and support vector machine for classification into the classification model. The classification error rate is used as the fitness function of quantum particle swarm optimization. The classification performance of quantum particle swarm optimization based CSP algorithm for joint selection of frequency band and time segment is evaluated by comparing with other three CSP algorithms using either fixed frequency band and time segment or fixed time segment and the frequency band selected by particle swarm optimization and quantum-behaved particle swarm optimization, on two MI data sets with different number of channels and trials. Experimental results suggest that the proposed algorithm outperforms the other three algorithms in terms of classification error rate. Across all subjects from the two data sets, the averaged error rate of the proposed algorithm was 7.45%, 2.97% and 2.05% lower than the CSP with fixed frequency band and time segment, that with selected frequency bands by particle swarm optimization and that with selected bands by quantum particle swarm optimization. The proposed algorithm can facilitate the real-world application of BCIs.

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total $\mathrm{\text{power}}=1.722$$\mu$W, $\mathrm{\text{delay}}=213$ps, $\mathrm{\text{PDP}}=0.3668$fJ, $\mathrm{\text{EDP}}=78.1285\times 10^{-27}$Js, $\mathrm{\text{area}}=36.59$$\mu$m², and $\mathrm{\text{PSNR}}=26.4292$dB. And the AFA2 has the total $\mathrm{\text{power}}=1.924$$\mu$W, $\mathrm{\text{delay}}=215$ps, $\mathrm{\text{PDP}}=0.4136$fJ, $\mathrm{\text{EDP}}=88.924\times 10^{-27}$Js, $\mathrm{\text{area}}=33.264$$\mu$m², and $\mathrm{\text{PSNR}}=26.4292$dB.

A 26GHz low-noise amplifier (LNA) designed for 5G applications using 0.18$\mu$m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than $-$7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of $-$10dB. Due to the inductor added in feedback at the second stage. The $S_{21}$ obtained is 18.208dB at 26GHz with a noise figure (NF) of 2.8dB. The power supply given to the LNA is 1.8V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-$2^r$ arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with $4:2$ compressors. This proposed architecture is implemented by using Radix-$2^r$-based multiplier and $4:2$ compressor architectures for achieving better improvement in the critical path delay. The Radix-$2^r$-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

In this paper, a high-frequency AC-link DC–AC converter is presented with detailed analysis. This converter is used as an interface between a dc power source and a grid. The studied converter is a universal power converter which consists of two bridges separated by an AC-link; each bridge is connected to a source or it feeds a load. The link of this converter contains a parallel pair inductance-capacitor. The inductance is used to stock/supply energy and for the link capacitor, it allows to perform soft switching during turning on/turning off of the switches. The studied converter has considerable advantages compared to the other topologies. Its fundamental properties are, especially, the compactness, reliability and efficiency which it ensures. Also, it guarantees longer lifetime and the possibility to transfer power in the two power flow directions. In this talk, the principles of the ac-link inverter operation are clearly explained in this paper. Simulation results, under MATLAB/SIMULINK, are shown to validate the correct operation and the efficiency of the proposed converter topology. The control algorithm is, also, experimentally implemented using a dSPACE 1104 control board.

This paper proposes a model to yield power from the low-power sources like microbial fuel cell (MFC). The structure of the MFC with a suitable energy storage unit is proposed and discussed in detail. The prototype of the MFC model with the charge pump (switched-capacitor) circuit is implemented and tested for an output voltage of 5V. Additionally, a novel high-step-up converter is suggested for the low-power applications. It employs a passive switched-inductor–capacitor cell (PSLC), which makes the switching of the LC network simple. This high-gain converter is derived by replacing the diode in the primary switched inductor cell with a capacitor. Compared to several topologies with similar voltage conversion ratio in the literature, the derived converter can achieve high voltage gain with the lesser component count. This study directs to propose a compact and lightweight DC–DC converter. Since the suggested topology is for low-power applications, a 5-W prototype is tested. The implemented setup is most appropriate for microbial fuel cell application, which is closely related to environmental stewardship.

A new study imitating the design and implementation of single-input–single-output (SISO) filters as bilateral filters has been presented in this paper. Second generation current controlled current conveyor (CCCII), being a popular low power active element was considered for the realization of the proposed design. Complete design, analysis and implementation of the voltage mode SISO filter was done using only two CCCII’s and two passive parasitic components. The striking feature of this work is that the proposed design can be made to work at either the input node or the output node, as well as in the cases; the change of direction changes the filter into an inverse filter and buffer filter. Basic filter applications like low-pass, high-pass, band-pass and band-stop were aimed to check the uniformity of the proposed design at different frequencies. Results perceived from the simulation study were fare enough on both the side nodes of the proposed design. Categorically, the circuit can be aimed to work in lieu of a filter transceiver. The consistency of the circuit was analyzed by the nodal analysis. Whereas the working performance was enormously analyzed and evaluated during the simulation analysis. The proposed design was simulated in HSPICE tool to exhibit and exploit the delivery, using the 45nm predictive technology model (PTM) parameters, with $\pm 1$V rail to rail voltages. Maximum power consumption of the circuit is around 138.5$\mu$W. Finally, the design was also implemented in Cadence Virtuoso using 40nm SMIC parameters.

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework.

Many applications including power trading and planning require the accurate estimation of solar power in real time. As the power output of the solar panels degrades over the time period, so its real-time estimation is tough without the degradation parameter. In the proposed method, the effect of degradation in terms of performance ratio is incorporated along with other meteorological parameters. The degradation is calculated in real time using the clustering-based technique without physical inspection on site. Initially, the power is estimated using Support Vector Regression (SVR) model with the meteorological parameters. The estimation is further fine-tuned in sync with the degradation rate. The model is validated on the real data (Meteorological parameters and Solar power) procured from the solar plant. After refinement, the estimation results show significant improvement in terms of statistical measures. Now, the estimation accuracy in terms of coefficient of determination R² is 92% and the error metrics normalized root mean square error (NMRSE), mean absolute percentage error (MAPE), root mean square error (RMSE) are 7.13, 5.92 and 14.54, respectively.

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.

This paper presents a system, AscentX, for labeled data creation and training with active supervision. The aim of system is that it makes collecting data and training models easier. We integrate semi-supervised learning and active learning as well as crowdsourcing learning paradigms. We design a web-based interface for labeling examples based on Python-Django and incorporate our proposed algorithms into it, including semi-supervised classification algorithms, semi-supervised clustering algorithms and with application to data filtering. Moreover, we provide the interfaces for future development including standard datasets attaching, algorithms and active learning models plunging. The system supports the visualization of labeling the examples and analyzing the results of algorithms, which is user-friendly for human annotator. We experimentally verify that AscentX achieves comparable performance to the state-of-the-art systems, using real-life (crawling web data) and benchmark datasets.

Person Re-ID is challenged by background clutter, body misalignment and part missing. In this paper, we propose a reliable part-based multiple levels attention deep network to learn multiple scales salience representation. In particular, person alignment and key point detection are sequentially carried out to locate three relative stable body components, then fused attention (FA) mode is designed to capture the fine-grained salient features from effective spatial of valuable channels of each part, regional attention mode is succeeded to weight the importance of different parts for highlighting the representative parts while suppressing the valueless ones. A late fusion-based multiple-task loss is finally adopted to further optimize the valuable feature representation. Experimental results demonstrate that the proposed method achieves state-of-the-art performances on three challenging benchmarks: Market-1501, DukeMTMC-reID and CUHK03.

In this paper, a novel approach to accelerate parameter extraction process of surface-potential-based (PSP) MOSFET model is presented for the submicron MOS transistor. To reduce the computational time, Field Programmable Gate Array (FPGA) implementation of PSP model library — SiMKit is demonstrated using Xilinx’s Zynq $\mathrm{\text{Ultrascale}}+\mathrm{\text{MPSoC}}$ (Multi-processor System-on-Chip) platform. Parameter extraction is carried out using Particle Swarm Optimization (PSO) algorithm for 65nm technology nMOS devices. With the available measurement data, 32 various PSP model parameters are extracted. Experimental results validate the performance and accuracy of parameter extraction by achieving Root Mean Square Error below 10% for various current–voltage characteristics of nMOS device. 41.57% acceleration in execution time for extraction process is achieved by Zynq $\mathrm{\text{Ultrascale}}+\mathrm{\text{MPSoC}}$ platform compared to the conventional computer-based software approach. In addition, various design optimization directives are explored, and their performances are compared as a part of RTL generation of SiMKit.