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We propose schemes for binary adder, subtractor and parity checker using optical logic gates. These schemes could be useful for calculations using optical systems. Utilizing optical logic gates, we can achieve functions of binary adder, subtractor and parity checker of high-speed optical signals. Due to two-photon absorption in the wetting layer, quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI) can work as high data rate optical logic gates. The simulated result supports the idea that it is possible to realize all-optical binary adder, subtractor and parity checker at high optical signal rates.

An all-optical data comparator with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) is proposed. The paper describes the all-optical data comparator by using a set of all-optical full-adder and optical switch. Comparison between two binary data is required in many data processing systems. It is sometimes necessary to know whether a binary number is greater than, equal to, or less than another number. The all-optical data comparator can be used to perform a fast central processor unit using optical hardware components. In this present communication, we have tried to exploit the advantages of TOAD-based switch to design an integrated all-optical circuit which can perform data comparison operations.

In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Different reforms are performed in multiplier architecture. In the first step of multiplier operator, a novel radix-16 modified Booth encoder is presented which reduces the number of partial products efficiently. In this research, we present a new algorithm for partial product reduction in multiplication operations. The algorithm is based on the implementation of compressor elements by means of carry network. The structure of these compressors into reduction trees takes advantage of the modified Wallace tree for integration of adder cells and provides an alternative to conventional operator methods. We show several reduction techniques that illustrate the proposed method and describe carry-skip examples that combine dynamic CMOS with classic conventional compressors in order to modify each scheme. In network multiplier, a novel low power high-speed adder cell is presented which uses 14 transistors in its structure. Critical path is minimized to reduce latency in whole operator architecture. Final adder of multiplier uses an optimized carry hybrid adder. The presented final adder network uses dynamic CMOS technology. It sums two final operands in a very efficient way, which has significant effect in operator structure. Presented multiplier reduces latency by 12%, decreases transistor count by 8% and modifies noise problem in an efficient way in comparison with other structures.

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90nm CMOS technology and 0.9V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

Critical constituent gates are first detected and graded based on their individual impact of an error in the outputs. This brings in the idea of practical reliability analysis metric. Then, the approximation of arithmetic circuits by random logic applied to least significant gates is introduced. The 74283 fast adder is used as an example to illustrate the feasibility of the proposed methods. Simulation results show the potential efficient application of the proposed reliability analysis metric and approximation method.

In this work, the design of the diminished-1 modulo $2^n+1$ adders, subtractors and adders/subtractors are examined. Some of the existing modulo $2^n+1$ adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

This paper explores the design and analysis of 20nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1GHz with high driving current and low power.

Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems’ most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder.

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16nm MOS-GNRFET model.

The continuous increment in the performance of classical computers has been driven to its limit. New ways are studied to avoid this oncoming bottleneck and many answers can be found. An example is the Belousov–Zhabotinsky (BZ) reaction which includes some fundamental and essential characteristics that attract chemists, biologists, and computer scientists. Interaction of excitation wave-fronts in BZ system, can be interpreted in terms of logical gates and applied in the design of unconventional hardware components. Logic gates and other more complicated components have been already proposed using different topologies and particular characteristics. In this study, the inherent parallelism and simplicity of Cellular Automata (CAs) modeling is combined with an Oregonator model of light-sensitive version of BZ reaction. The resulting parallel and computationally-inexpensive model has the ability to simulate a topology that can be considered as a one-bit full adder digital component towards the design of an Arithmetic Logic Unit (ALU).

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs’ correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs.

A new feature descriptor called local bit plane-based dissimilarities and adder pattern (LBPDAP) is proposed in this paper for content-based computed tomography (CT) image retrieval. To compute the descriptor, the bit planes of the input image are first extracted. For each pixel of an image, these bit planes are then locally encoded using an adder which combines the center-neighbor dissimilarity information and the neighbor–neighbor mutual dissimilarity information in each bit plane. The encoded bit plane values corresponding to each center pixel are finally compared with the intensity of the center pixel to compute the proposed LBPDAP. In order to limit the feature dimensions, we have considered only four most significant bit planes for LBPDAP computations as the higher bit planes contain more significant visual texture information. The proposed descriptor is low dimensional and experimental results on widely accepted NEMA and TCIA-CT image databases demonstrate better retrieval efficiency of LBPDAP over many recent local pattern-based approaches.

We propose schemes for binary adder, subtractor and parity checker using optical logic gates. These schemes could be useful for calculations using optical systems. Utilizing optical logic gates, we can achieve functions of binary adder, subtractor and parity checker of high-speed optical signals. Due to two-photon absorption in the wetting layer, quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI) can work as high data rate optical logic gates. The simulated result supports the idea that it is possible to realize all-optical binary adder, subtractor and parity checker at high optical signal rates.