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This paper presented a multiplier-less memcapacitor emulator circuit that is implemented without using a memristor mutator. The proposed circuit is a charge-controlled memcapacitor built with analog blocks. Comparatively, this circuit uses fewer active–passive elements, where all passive elements are grounded. In addition, the most advantageous feature is its tuning which can be done externally by electronic means. Also, the proposed circuit layout has been drawn with minimum metal routing, optimum floor planning, and DRC and LVS checks. The circuit behavior is justified through various simulations in the Cadence Virtuoso-Spectre tool with 180-nm CMOS parameters, and the operating frequency of the proposed circuit is up to 4KHz. In addition, theoretical and simulated results are proven through experimental verification using off-the-shelf IC.

A review of the two types of circulators using Operational Amplifiers (OA) with detailed comparison is given. Novel active circulator circuits using Current Conveyors (CCII) and Current Feedback Operational Amplifiers (CFOA) and Differential Voltage Current Conveyor (DVCC) are introduced. The proposed CCII circulator circuit uses six CCIIs and three floating resistors. Two different circulator types using the CFOA are given. A circulator circuit which uses three DVCCs and has the advantage of using three grounded resistors is also introduced.

Spice simulation results using 0.5 μm CMOS transistors are included to support the theoretical analysis and demonstrate comparisons among the different types of circulators.

Two new minimum passive component oscillators using inverting current conveyor (ICCII–) acting as a voltage negative impedance converter are generated from the Sallen Key low-pass and high-pass filters. It is also shown that the Sallen Key low-pass, high-pass, and band-pass filters are the origin of the three minimum component oscillators using the current conveyor acting as a current negative impedance converter. In addition, it is also shown that the Sallen Key high-pass and band-pass filters are the origin of the two minimum component oscillators using single input single output transconductance amplifier as the active element. Although this paper is considered partially a review paper it includes new generation methods and new minimum component oscillator circuit realizations. Simulation results for the new oscillators using ICCII– are included.

In this work, a wideband and high-performance CMOS implementation of 2nd-generation current conveyor (CCII) is proposed. The proposed circuit is composed of a high performance voltage follower stage which is based on differential pairs to provide high voltage swings on input and output ports and a current follower stage. It is shown that the proposed voltage follower stage can be used to implement high performance 1st and 3rd-generation current conveyors (CCI and CCIII, respectively) that have very small equivalent impedances on ports X, high equivalent impedances on ports Y and Z and also high-valued voltage and current transfer bandwidths. 2nd and 3rd order filter circuits as well as a half-wave rectifier circuit are given to show the performance and usefulness of the proposed current conveyor circuits. The simulation and experimental results are given to verify the theoretical analyses.

This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are deduced in terms of the fractional-order parameters. The extra degree of freedom provided by the fractional-order elements increases the design flexibility. Eight special cases including the integer case are illustrated with their numerical discussions. Three different phases are produced with fixed sum of $2\pi$ which can be completely controlled by fractional-order elements. A general design procedure is introduced to design an oscillator with a specific phase and frequency. Two general design cases are discussed based on exploiting the degrees of freedom introduced by the fractional order to obtain the required design. Spice circuit simulations with experimental results for some special cases are presented to validate the theoretical findings.

In this work, novel swarm optimization algorithm based on the Artificial Bee Colony (ABC) algorithm called Enhanced Artificial Bee Colony (EABC) algorithm is proposed for the design and optimization of the analog CMOS circuits. The new search strategies adopted improve overall performance of the proposed algorithm. The performance of EABC algorithm is compared with other competitive algorithms such as ABC, GABC (G-best Artificial Bee Colony Algorithm) and MABC (Modified Artificial Bee Colony Algorithm) by designing three CMOS circuits; Two-stage operational amplifier, low-voltage bulk driven OTA and second generation low-voltage current conveyor in 0.13 $\mu$m and 0.09$\mu$m CMOS technologies. The obtained results clearly indicate that the performance of EABC algorithm is better than other mentioned algorithms and it can be an effective approach for the automatic design of the analog CMOS circuits.

This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ($g_m∕I_D$) technique for low-voltage (LV) and low-power (LP) applications. The $g_m∕I_D$ technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ($D_{\mathrm{\text{CNT}}}$) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at $\pm$0.5V and has 172$\mu$W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ($I_Z∕I_X)\text{ i.e. }34.3$GHz as well as voltage gain ($V_X∕V_Y)\text{ i.e. }35.1$GHz.