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This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm². With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

Nowadays time-to-digital converter (TDC) is the most popular method of time measurement in many applications. The CMOS process, which gains an advantage over Emitter Coupled Logic (ECL) and GaAs in cost and portability, provides sufficient space for TDC development. This paper presents a review of CMOS TDCs classified by circuit topologies and performance. For each TDC structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of TDCs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of TDC and the possible tendency for future work in summary.

Features of transition from regular types of oscillations to chaos in dynamic systems with finite and infinite dimensionality of phase space have been discussed. It has been found that for some types of nonlinearity, transition to the chaotic motion in these systems occurs according to the identical autoparametric scenario. The sequence of bifurcation phenomena looks as follows: equilibrium state ⇒ limit cycle ⇒ semitorus ⇒ strange attractor. On the basis of the results of numerical simulation a conclusion was made about the typical nature of such a scenario. The results of numerical calculations are confirmed by results of physical experiments carried out on the base of radiophysical self-oscillatory systems.

In binary Differential Chaos Shift Keying (DCSK), the reference and information bearing chaotic wavelets are transmitted in two consecutive time slots. This TDMA approach provides two independent channels for the transmission of reference and information bearing wavelets but requires a delay component both in the modulator and demodulator circuits, furthermore, it halves the data attainable data rate. The wideband Radio Frequency (RF) delay lines at receiver are extremely difficult to implement with CMOS technology, therefore, the DCSK modulation cannot be exploited in many applications, such as ultra-wideband. To avoid the use of wideband RF delay lines at receiver, an alternative solution is proposed here where both the reference and information bearing wavelets are sent in the same time slot. The two wavelets are separated by Walsh codes instead of time delay. The new modulator and demodulator configurations are given, analytical expressions for the Bit Error Rate (BER) are derived and the derived BER expressions are verified by computer simulations over Additive White Gaussian Noise (AWGN) and multipath Rayleigh fading channels.

In this paper, a new Cellular Automata (CA) Model, named Cellular Automata with Random Memory, has been introduced. The new model is in fact, constructed by randomizing the choosing memory operation of a Cellular Automata with memory. Therefore, the model has a potential usage for application like Random Number Generators, Physical Unclonable Functions. The introduced model and other CA models are represented in an abstract form. Delay lines comprising sequentially connected logic gates are introduced in the implementation of the memory part of the introduced model. Due to the process of variations and jitter effect, the delay line becomes beneficial in the implementation of the proposed Cellular Automata with Random Memory. The introduced model is implemented on a FPGA using delay lines and also using other alternative methods.

This paper is devoted to analysis and synthesis of controllable clock generator. Here it is mathematically rigorously shown that RC-chain can be used as a delay line in the design of controllable clock generators. Bifurcation analysis of one-dimensional discrete model of controllable clock generator is done.