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This paper presented a multiplier-less memcapacitor emulator circuit that is implemented without using a memristor mutator. The proposed circuit is a charge-controlled memcapacitor built with analog blocks. Comparatively, this circuit uses fewer active–passive elements, where all passive elements are grounded. In addition, the most advantageous feature is its tuning which can be done externally by electronic means. Also, the proposed circuit layout has been drawn with minimum metal routing, optimum floor planning, and DRC and LVS checks. The circuit behavior is justified through various simulations in the Cadence Virtuoso-Spectre tool with 180-nm CMOS parameters, and the operating frequency of the proposed circuit is up to 4KHz. In addition, theoretical and simulated results are proven through experimental verification using off-the-shelf IC.

Introducing the memcapacitor into the Cellular Neural Network (CNN), the Memcapacitor-Cellular Neural Network (MC-CNN) model with infinitely many equilibrium points is constructed. A series of dynamical behaviors of the MC-CNN are investigated by various nonlinear system analysis means. It is shown that the system has a large maximum Lyapunov exponent in a specific parameter range. And with the variation of parameters, the system is able to produce many different phase trajectories of the attractor. Multistability is also found in the system. The pseudo-randomness of the MC-CNN is calculated by Spectral Entropy (SE) complexity algorithm. The final hardware results proves the physical realizability of the system. The MC-CNN model is intended to provide guidance for neural networks and cryptographic strategies based on the memcapacitor.

Many literatures have discussed fractional order memristor and memcapacitor-based chaotic oscillators but the entire oscillator model is considered to be of fractional order. My interest is to propose a nonlinear oscillator with considering only the memcapacitor element of fractional order. Hence, I propose a fractional order memcapacitor (FMC)-based novel chaotic oscillator. The complete mathematical model for the proposed oscillator is derived and presented in this paper. The dimensionless state equations are then analyzed by using the equilibrium points and their stability, Eigen values, Kaplan–Yorke dimensions and Lyapunov exponents. To understand the complete dynamical behavior, bifurcation graphs are obtained and presented. Finally, the proposed fractional memcapacitor oscillator is implemented by using the shelf components.

Memory circuit elements are of interest due to their use in different fields of science and technology. In this research, a new multi-outputs operational transconductance amplifiers (MO-OTA)-based memcapacitor emulator is proposed. The proposed emulator employs two OTAs, two capacitors, two resistors and an analog multiplier. The memcapacitor emulator circuit has electronically tunability property. Charge value of the memcapacitor can be adjusted by changing the transconductance $g_m$ value with the biasing current of the MO-OTA or frequency value of the input signal. In order to analyze the performance of the proposed circuit, memcapacitor emulator is simulated in 0.18$\mu$m TSMC CMOS process using LTSPICE and the simulation results are demonstrated.

In this paper, two simple circuits are presented to emulate both memcapacitor and meminductor circuit elements. The emulation of these components has crucial importance since obtaining these high-order elements from markets is difficult when compared to resistor, capacitor and inductor. For this reason, we proposed Multi-Output Operational Transconductance Amplifier (MO-OTA)-based electronically controllable memcapacitor and meminductor circuits. To operate the MOS transistor as a capacitor, drain and source terminals are connected to each other. The memcapacitor behavior is obtained by driving the connected terminals with suitable voltage values. Only a few active and grounded passive components which are found in markets easily are used to emulate meminductive behavior. Furthermore, all passive elements in the circuit are grounded. All simulation results for memcapacitor and meminductor emulators are obtained successfully when compared to previous studies. For all analyses, MO-OTA is laid using the Cadence Spectre Analog Environment with TSMC 0.18$\mu$m process parameters and occupied a layout area of only 86.21$\mu \mathrm{\text{m}}\times 34.67\mu$m.

For the first time, a new memristor emulator structure using a single four-terminal floating nullor (FTFN) and a transconductance stage has been presented with tunable circuit configuration. Along with that the circuit requires only a single grounded capacitance and two external MOS transistors to realize both incremental and decremental types of memductance functions. The use of the FTFN block has been demonstrated for the first time to build such a compact memristor emulator, which fully utilizes the employed circuit resources. The wide-band operating frequency range (1 kHz–3 MHz) is another attractive feature of the proposed emulator. Moreover, the mutation of the proposed memristor emulator into meminductor and memcapacitor emulators is also presented by the mutators based on FTFN. All the presented circuits have been tested by performing simulations using PSPICE with 0.18-$\mu$m CMOS technology. The generated simulation results clearly show the ideal nonvolatile nature of the realized memristor, which has also been utilized in an op-amp-based circuit designed to exhibit associative learning phenomena. The proposed FTFN-based memristor has been implemented using commercially available ICs, LM13700, and AD844, and the generated PHL plot is discussed.

This paper presents a floating meminductor emulator circuit using a voltage differencing inverted buffered amplifier (VDIBA), current follower (CF), and two grounded capacitors. The parasitic resistance at the input terminal of the current follower has been utilized. The idea of implementing a meminductor emulator is simple and works on the principle of putting memory inside the active inductor circuit. A capacitor (memory element) has been charged by the current flowing through the active inductor circuit. Therefore, the proposed meminductor emulator can be viewed as an active inductor circuit having memory inside it. The proposed floating meminductor emulator works over a significant range of frequencies and satisfies all the characteristics of a meminductor. The meminductor emulator has been realized and simulated in the LTspice simulation tool using TSMC’s 180-nm CMOS technology parameters. A chaotic oscillator circuit has been realized using the proposed meminductor emulator to verify its performance. The results obtained for the chaotic oscillators are found to be satisfactory and thus verify the performance of the proposed meminductor emulator.

In this paper, we show that the dynamics of any memristor circuits can be simulated by a corresponding "dual" nonlinear RLC circuit where the memristor is substituted by a nonlinear resistor. They are in one-to-one correspondence, that is, they are duals of each other. We also propose a method for synchronizing these dual dynamic nonlinear circuits. We next define memory elements which can be characterized by charge and flux. The memory-element circuits can also be simulated by their corresponding dual nonlinear RLC circuits. We then define 2-terminal elements which are characterized by complementary pair of signals, and study them from the view point of one-to-one correspondence. We finally show an example of 2-terminal elements such that the terminal voltage and current are identical, and their time-derivatives of any order are also identical, however, their time-integrals are different. That is, these 2-terminal elements are in one-to-one correspondence except for the time-integral signals.

An efficient method to build the expandable circuits of memcapacitor (MC) emulator in various configurations is proposed using our expandable memristor (MR) emulator. Most of the previous studies succeeded in designing only a stand-alone memcapacitor emulator. In this study, the expandable architecture of memcapacitor emulator is addressed, where the connectivity and interoperability are the main concern. It is shown that the memcapacitor circuits can be built only with memristors together with a single mutator, which is connected after each input source. Examples of serial, parallel and hybrid memcapacitor circuits are demonstrated in this paper. Also, it is shown that complicated circuits of Wye (Y) and Delta (Δ) memcapacitor connections with multiple input sources can be built with the proposed memcapacitor emulator. Various simulation results showing the proper operations of the proposed mutator-based expandable memcapacitor emulators are included in this paper.

Memristor, the missing fourth passive circuit element predicted forty years ago by Chua was recognized as a nanoscale device in 2008 by researchers of a H. P. Laboratory. Recently the notion of memristive systems was extended to capacitive and inductive elements, namely, memcapacitor and meminductor whose properties depend on the state and history of the system. In this paper, we use fractional calculus to generalize and provide a mathematical paradigm for describing the behavior of such elements with memory. In this framework, we extend Ohm's law to the generalized Ohm's law and prove it.

In this paper, we show that parasitic elements have a significant effect on the dynamics of memristor circuits. We first show that certain $2$-terminal elements such as memristors, memcapacitors, and meminductors can be used as nonvolatile memories, if the principle of conservation of state variables hold by open-circuiting, or short-circuiting, their terminals. We also show that a passive memristor with a strictly-increasing constitutive relation will eventually lose its stored flux when we switch off the power if there is a parasitic capacitance across the memristor. Similarly, a memcapacitor (resp., meminductor) with a positive memcapacitance (resp., meminductance) will eventually lose their stored physical states when we switch off the power, if it is connected to a parasitic resistance. We then show that the discontinuous jump that circuit engineers assumed to occur at impasse points of memristor circuits contradicts the principles of conservation of charge and flux at the time of the discontinuous jump. A parasitic element can be used to break an impasse point, resulting in the emergence of a continuous oscillation in the circuit. We also define a distance, a diameter, and a dimension, for each circuit element in order to measure the complexity order of the parasitic elements. They can be used to find higher-order parasitic elements which can break impasse points. Furthermore, we derived a memristor-based Chua’s circuit from a three-element circuit containing a memristor by connecting two parasitic memcapacitances to break the impasse points. We finally show that a higher-order parasitic element can be used for breaking the impasse points on two-dimensional and three-dimensional constrained spaces.

Detecting chaos in heavy-noise environments is an important issue in many fields of science and engineering. In this paper, first, a new criterion is proposed to recognize chaos from noise based on the distribution of energy. Then, a new method based on stationary wavelet transform (SWT) is presented for chaos detection that is recommended for data that contain more than 60% noise. This method is dependent on the distribution of signal’s energy in different frequency bands based on SWT for chaos detection which is robust to noisy environments. In this method, the effect of white noise and colored noise on the chaotic system is considered. As a case study, the proposed method is applied to detect chaos in two different oscillators based on memristor and memcapacitor. The simulation results are used to display the main points of the paper.

Memory elements, including memristor, memcapacitor, meminductor and second-order memristor, have been widely exploited recently to realize circuit systems for a broad scope of applications. This paper introduces a phasor analysis method for memory elements to help with the understanding of the complex nonlinear phenomena in circuits with memory elements. With the proposed method, all different memory elements could be described in a unified form and the series-connected circuit with memristor, memcapacitor, meminductor and second-order memristor could be simply modeled as one variable ${Ż}_M$. Thus, the phasor vectors provided a way to conveniently calculate the $v$–$i$ relation of different memory elements and to clearly understand the similarities and differences between all memory elements. Then some interesting phenomena were introduced when combining different memory elements. Moreover, a specific ${Ż}_M$ with certain $v$–$i$ relations could be easily obtained with the method. And through the inverse calculation, the specific ${Ż}_M$ could be decomposed to a certain combination of memory elements. Meanwhile, the parameters of ${Ż}_M$ in the phasor domain were analyzed. Furthermore, the frequency characteristic for a $R_M{L}_M{C}_M$ circuit could be easily analyzed with the method and a particular series resonance was introduced.

In this paper, a new memristor model and a new memcapacitor model are proposed. Based on the two models, a simple chaotic circuit is constructed. Due to the special characteristics of the memristor and memcapacitor, the proposed circuit has two-dimensional normally hyperbolic manifolds of equilibria, and nonparametric bifurcation can occur when the conditions supporting the normal hyperbolicity of such manifolds are not satisfied. By adding a nonlinear controller to the proposed circuit, an anti-controlled system is realized, which has hyperchaotic dynamic behaviors under some suitable control parameters. The stability of equilibrium points and dynamic properties of the original system and the anti-controlled system are explored by Lyapunov exponents, bifurcation diagrams and so on. Furthermore, the anti-controlled system is applied to design a random sequence generator on digital signal processor platform.

Memcapacitors (MCs) are promising candidates for the future design of low-power integrated neuromorphic computing systems, with particular emphasis on dynamical spiking neuron models that exhibit rich temporal behaviors. We present a novel floating flux-controlled MC that is designed using only three current feedback amplifiers, one analog multiplier, one capacitor and one resistor. Compared with existing floating MC emulators, our proposed design has a simpler structure without the need for DC biasing voltage sources, and can operate at higher working frequencies, and therefore enabling rapid prototyping of applied MC circuits for experimental verification of large-scale MC arrays. The consistency of the theoretical analysis, simulation and experimental results confirms the correctness and practicability of this new memcapacitor emulator. To further demonstrate a potential use of our MC, in this work, we apply the MC as the first parameterizable leaky integrator for spiking neuron through simulation and experiments. The intrinsic tunable capacitance of the MC can bring about novel short-term memory dynamics to neuronal circuits by dynamically modifying the membrane time constant on-the-fly, which ultimately resembles long-term potentiation, and can thus offer longer term memory.

Our results highlight the potential for integrating heterogeneous spiking neural networks with richer temporal dynamics that rely on MC-based circuits to further the capability of neuromorphic computing.

As the fourth fundamental circuit element, Memristor has been achieving lots of attention since its realization. This paper presents the analysis of memcapacitive and meminductive circuit and investigate the response of the circuit to periodic and aperiodic input voltage signals. The simulation results show that the periodic input would change the memcapacitance sharply while the aperiodic input will not change the state of the memcapacitor. Similar results have been observed in meminductive circuit and we have also analysed this phenomenon.