Narrow Results

This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are deduced in terms of the fractional-order parameters. The extra degree of freedom provided by the fractional-order elements increases the design flexibility. Eight special cases including the integer case are illustrated with their numerical discussions. Three different phases are produced with fixed sum of $2\pi$ which can be completely controlled by fractional-order elements. A general design procedure is introduced to design an oscillator with a specific phase and frequency. Two general design cases are discussed based on exploiting the degrees of freedom introduced by the fractional order to obtain the required design. Spice circuit simulations with experimental results for some special cases are presented to validate the theoretical findings.

This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty issues. PSO is a robust optimization method but suffers from sub-optimality problem. This paper effectively hybridizes the random PSO and DE to remove the limitations related to both the techniques individually. In this paper, RPSODE is employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained from RPSODE technique are validated in SPICE environment. SPICE-based simulation results justify that RPSODE is a much better technique than other formerly reported methods for the designs of the above mentioned circuits in terms of MOS area, gain, power dissipation, etc.

Due to the absence of commercially available fractional-order capacitors and inductors, their implementation can be performed using fractional-order differentiators and integrators, respectively, combined with a voltage-to-current conversion stage. The transfer function of fractional-order differentiators and integrators can be approximated through the utilization of appropriate integer-order transfer functions. In order to achieve that, the Continued Fraction Expansion as well as the Oustaloup’s approximations can be utilized. The accuracy, in terms of magnitude and phase response, of transfer functions of differentiators/integrators derived through the employment of the aforementioned approximations, is very important factor for achieving high performance approximation of the fractional-order elements. A comparative study of the accuracy offered by the Continued Fraction Expansion and the Oustaloup’s approximation is performed in this paper. As a next step, the corresponding implementations of the emulators of the fractional-order elements, derived using fundamental active cells such as operational amplifiers, operational transconductance amplifiers, current conveyors, and current feedback operational amplifiers realized in commercially available discrete-component IC form, are compared in terms of the most important performance characteristics. The most suitable of them are further compared using the OrCAD PSpice software.

Graphene Field Effect Transistor (GFET) is a promising candidate for future high performance applications in the beyond CMOS roadmap for analog circuit applications. This paper presents a Verilog-A implementation of a monolayer graphene field-effect transistor (mGFET) model. The study of characteristic curves is carried out using advanced design system (ADS) tools. Validation of the model through comparison with measurements from the characteristic curves is carried out using Silvaco TCAD tools. Finally, the mGFET is used to design a GFET-based operational amplifier (Op-Amp). The GFET Op-Amp performances are tuned in term of the graphene channel length in order to obtain a reasonable gain and bandwidth. The main characteristics of the Op-Amp performance are compared with 0.18$\mu$m CMOS technology.

This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ($g_m∕I_D$) technique for low-voltage (LV) and low-power (LP) applications. The $g_m∕I_D$ technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ($D_{\mathrm{\text{CNT}}}$) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at $\pm$0.5V and has 172$\mu$W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ($I_Z∕I_X)\text{ i.e. }34.3$GHz as well as voltage gain ($V_X∕V_Y)\text{ i.e. }35.1$GHz.

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1V supply. The circuit draws a total static current of 295$\mu$A and occupies 5000$\mu$m² of silicon area.

For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its adverse effect on the op-amp’s differential-mode gain has not been investigated much. The explanation for this effect is the SC-CMFB-induced equivalent resistive loading, and this is particularly significant in amplifiers like folded cascode which are intended to provide a high gain. This issue of drop in op-amp dc gain because of SC-CMFB, and the consequence on the realization of continuous-time and discrete-time forms of integrators utilizing such amplifiers is the topic of discussion in this paper. Relevant analytical derivations and circuit simulations at the transistor level are provided. A couple of design guidelines and circuit topologies for minimizing the loading-induced gain reduction are also presented.

Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 μm BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of 62° for a load capacitance of 2 pF. Output voltage swings are ±3.71 V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162 μm × 200.82 μm. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.

A power-efficient second-order no-capacitor feedforward (NCFF) op-amp has been designed in 180nm CMOS process. To attain high gain and better common mode rejection, cross-coupled loading network has been used in each differential stage. The designed op-amp achieves over 40dB gain up to 400MHz and over 10dB open loop gain up to 4GHz with 0.87mW power consumption. It is suitable for application in continuous-time delta-sigma modulator (CT $\mathrm{\Delta }\mathrm{\Sigma }$M) with sampling frequency in GHz range.

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.