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For the requirement of power management controller chips, a wide supply range bandgap voltage reference circuit is presented. The preregulated circuit based on the regulation characteristic of zener diode extends the supply range and increases power supply rejection ratio (PSRR). Compensated by the base-emitter voltage (V_BE) linearization technique, the temperature stability of the bandgap circuit is improved further. The proposed circuit is implemented in a 0.4 μm bipolar CMOS DMOS (BCD) process and Spice simulation has been done for validation. The results of simulation and test show that the supply range of this circuit can reach 7.2 V to 40 V and 159 μV/V of supply voltage dependence; the temperature coefficient is just 3.5 ppm/°C over a wide temperature of -40°C to 125°C and PSRR is up to -94 dB at 1 kHz. For the perfective performance, this circuit can be used in wide temperature and wide supply range integrated circuit design.

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ($\Delta \Sigma$) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18$\mu$m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5pF to 6.5pF with a worst case PSRR of 0.5% from 0.3V to 0.42V (0.67% from 0.3V to 0.6V). With a 3.5pF input capacitance and a 0.3V supply, the $\Delta \Sigma$ stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2fF/LSB) with a conversion frequency of 371Hz. With an average power consumption of 40nW and a sampling frequency of 47.5kHz, a figure-of-merit (FoM) of 0.78pJ/conv-step is achieved.

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312mV with a temperature coefficient (TC) of 38.85ppm/^∘C over a wide temperature range of $-40^{\circ }$C to 125^∘C with a supply voltage of 0.8V. The line sensitivity is 0.027% $∕\mathrm{\text{V}}$ with a supply voltage ranging from 0.8V to 3V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as $-80.84$ and $-71.66$dB at 100Hz and 100kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027mm².

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85mV with a temperature coefficient of 29.5ppm/^∘C for the temperatures ranging from $-55^{\circ }$C to 125^∘C at a supply voltage of 0.8V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8V to 5V at nominal temperature (27^∘C). A PSRR of $-$91.69dB is observed for the frequencies ranging from 1Hz to 10kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1Hz and 10kHz are obtained as 2.37$\mu$V/$\surd$Hz and 45.26nV/$\surd$Hz, respectively.

This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2V and produces an output voltage of 1.2V. In simulations, the LDO regulator achieves 143-$\mu$ A quiescent current, $-$56-dB PSRR @ 1-kHz noise frequency and an output voltage drop of around 200mV for a load current step of 100mA. The LDO can provide a maximum load current of 200mA.

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.