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This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-V_P-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 μm CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 μW at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-μm 3.3 V BiCMOS technology.

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

This paper presents a multiscaling coefficient technique for convergence speed boosting in pipelined analog-to-digital converter (ADC) with noisy-signal-based gain error background calibration. By detecting the monotonicity of calculated gain error, the convergence process of the system can be divided into several phases. Each phase is then applied with different scaling coefficients, so rapid convergence speed and stable calibration system can be accomplished simultaneously. The time cost on convergence process can be reduced significantly, and stable calibration system has been simulated during the ADC's normal operation.

A pipelined analog-to-digital converter (ADC) that exhibits both power and area efficiencies is presented in this paper for ZigBee receiver applications. A combined opamp- and capacitor-sharing technique which presents a novel method to eliminate the memory effect is proposed. Fabricated in a 0.13-$\mu$m CMOS process, the prototype 7-bit 16-MS/s ADC occupies 0.16mm² active die area and achieves 41.9dB signal-to-noise-and-distortion ratio (SNDR), 52.1dB spurious-free dynamic rage (SFDR). The experimental results show that the figure of merit (FOM) is 1.12pJ/step and power dissipation is 1.82mW from a 1.2V supply.

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35$\mu$m CMOS AMS process technology with $3.3$V supply voltage and an input common-mode range of $1.15–2.15$V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of $32.32$mV with $2.49$mV 3$\sigma$ deviation, a slew rate of $8.29$V/ns with $0.45$V/ns 3$\sigma$ deviation, and a propagation delay of $4.16$ns with $0.15$ns 3$\sigma$ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of $63.01^{\circ }$, and a high-gain of $79.22$dB with $1.92^{\circ }$ and $4.86$dB 3$\sigma$, respectively, by using $1\text{pF}$ load capacitance.