Narrow Results

Cloud computing’s simulation and modeling capabilities are crucial for big data analysis in smart grid power; they are the key to finding practical insights, making the grid resilient, and improving energy management. Due to issues with data scalability and real-time analytics, advanced methods are required to extract useful information from the massive, ever-changing datasets produced by smart grids. This research proposed a Dynamic Resource Cloud-based Processing Analytics (DRC-PA), which integrates cloud-based processing and analytics with dynamic resource allocation algorithms. Computational resources must be able to adjust the changing grid circumstances, and DRC-PA ensures that big data analysis can scale as well. The DRC-PA method has several potential uses, including power grid optimization, anomaly detection, demand response, and predictive maintenance. Hence the proposed technique enables smart grids to proactively adjust to changing conditions, boosting resilience and sustainability in the energy ecosystem. A thorough simulation analysis is carried out using realistic circumstances within smart grids to confirm the usefulness of the DRC-PA approach. The methodology is described in the intangible, showing how DRC-PA is more efficient than traditional methods because it is more accurate, scalable, and responsive in real-time. In addition to resolving existing issues, the suggested method changes the face of contemporary energy systems by paving the way for innovations in grid optimization, decision assistance, and energy management.

Impulsivity is a multidimensional construct often associated with unfavorable outcomes. Previous studies have implicated several electroencephalography (EEG) indices to impulsiveness, but results are heterogeneous and inconsistent. Using a data-driven approach, we identified EEG power features for the prediction of self-reported impulsiveness. To this end, EEG signals of 56 individuals (18 low impulsive, 20 intermediate impulsive, 18 high impulsive) were recorded during a risk-taking task. Extracted EEG power features from 62 electrodes were fed into various machine learning classifiers to identify the most relevant band. Robustness of the classifier was varied by stratified $k$-fold cross validation. Alpha and beta band power showed best performance in the classification of impulsiveness (accuracy = 95.18% and 95.11%, respectively) using a random forest classifier. Subsequently, a sequential bidirectional feature selection algorithm was used to estimate the most relevant electrode sites. Results show that as little as 10 electrodes are sufficient to reliably classify impulsiveness using alpha band power ($f$-measure = 94.50%). Finally, the Shapley Additive exPlanations (SHAP) analysis approach was employed to reveal the individual EEG features that contributed most to the model’s output. Results indicate that frontal as well as posterior midline alpha power seems to be of most importance for the classification of impulsiveness.

We report on the investigation of an InAlN/GaN HEMT structure, delivering higher sheet carrier density than the commonly used AIGaN/GaN system. We achieved in a reproducible way more than 2 A/mm maximum drain current density for a gate length of 0.25 μm with unpassivated undoped devices realized on sapphire substrates. Small signal measurements yield a F_T = 31 GHz and F_MAX = 52 GHz, which illustrates the capability of these structures to operate at high frequencies. Moreover, the pulsed analysis indicates a more stable surface in the case of AlInN than that of AlGaN, attributed to the lattice matched growth of this barrier with 17% In content on GaN, avoiding strain piezo polarization in the material.

We report on the investigation of lattice matched InAlN/GaN MOS-HEMT structures prepared by thermal oxidation at 800 °C in oxygen atmosphere for two minutes. The gate leakage current was reduced by two orders of magnitude. Pulse measurements showed lag effects similar to what is observed for devices without oxidation, indicating a high quality native oxide. The MOS-HEMT showed no degradation in the small signal characteristics and yielded a power density of 5 W/mm at 30 V drain voltage at 10 GHz, power added efficiency of 42% and F_t and F_max of 42 and 61 GHz respectively, illustrating the capability of such MOS-HEMT to operate at high frequencies.

The construction of new electric power systems has led to a multiplication in the number of access nodes for electric power IoT information communication, accompanied by a deepening trend in business cloudification. However, due to the insufficient resource linkage and regulation capabilities of the electric power communication network on the cloud side, network side, and edge side, coupled with the lack of a convenient and unified cloud-network resource convergence and control mechanism, the existing electric power communication architecture is gradually finding it difficult to fully meet the demand for deterministic multi-service bearer. Therefore, it is necessary to evolve the original network equipment within the network toward a white box model, opening up interfaces for fine-grained sensing and full-area control, in order to provide more accurate and controllable network transmission services. In this paper, we first propose a cloud-network cooperative resource scheduling architecture for the electric power white box network. This architecture establishes a bearer network to achieve high consistency and cooperativeness of cloud-side end computing power through white box switches, uniformly schedules the global resources of the cloud-network convergence network, and improves the network service quality between cloud-side and side-side. Furthermore, we design a multi-dimensional re-source scheduling method for cloud-network synergy in the electric power white box network. This involves constructing a white box network virtualized heterogeneous resource (VHR) model and a heterogeneous resource control flow (HRCF) model. We transform the problem of merged deployment of service function chains (SFCs) into an SFC merger deployment problem by jointly controlling heterogeneous information, communication, storage, and arithmetic resources, along with the white box switch-specific pipelining resources in the white box network. We then carry out merger optimization of the same kind of function chains. Additionally, we propose a G-GS algorithm based on heuristic methods. Simulation results demonstrate that the method presented in this paper can significantly reduce the cost consumption of white box pipeline resources in the electric power white box network, thereby reducing the processing delay of SFC and improving the quality of electric power service bearing.

This paper develops a model in which a country, which only has access to a dirty technology for producing electric power in the short run, looks to expand its production in the long run by only permitting new power plants based on clean technology. The model mimics current reality in which major developing countries are being pushed by factors, such as the Paris Climate agreement of 2015 and the large burden of mortality and morbidity resulting from use of fossil fuels, to rely more on clean technologies. Our model shows how emissions and emission intensity of power output after the adoption of clean technologies are increasing in the targets for power production set by the government before availability of such technology and supply variables such as the wage rate and expenses on fixed capital, and decreasing in the tax on power production before the availability of clean technologies. Finally, it is seen that for low enough cost of the clean resource input, a country with a higher demand is able to set a higher target for production with the dirty technology when the clean technology is not available and yet achieves lower emissions and emission intensity in the long run.

The lift and power requirements of a model dragonfly in forward flight are studied, using the method of numerically solving the Navier-Stokes equations. The graph of power against flight speed is U-shaped, suggesting that a dragonfly might have a preferred cruising speed. Considerable variation in the relative phase between fore- and hindwings results in only very small change in power requirement. This suggests theat the forewing-hingwing interaction is weak and furthermore, might explain why phase angles ranging from to are employed by dragonflies in hovering and forward flight.

We study the performance optimization for mesoscopic thermoelectric generators (MTGs) with broken time-reversal symmetry by using an ecological criterion, and some specific properties of the thermoelectric system are further revealed. We discuss the working regimes of time-reversal symmetric mesoscopic (macroscopic) thermoelectric generators, and find that a larger thermodynamic efficiency can be obtained only when the Wiedemann–Franz (WF) law is strongly violated. Furthermore, a definite dependence of the optimal bound efficiency (power) on the asymmetry parameter and the generalized thermoelectric figure of merit is analytically determined, and it is found that the usual value $3{\eta }_c/4$ can be readily overcome. A larger efficiency can be obtained with the further enhancement of broken time-reversal symmetry, although the power output does not synchronize with efficiency. Interestingly, both the increase of the number $n$ of terminals and the external magnetic field open up the possibility to physically enhance the performance of thermoelectric generators, and the underlying physical origin of the improved energy conversion is also provided. The obtained results can contribute to a profound insight of thermodynamic performance for MTGs.

The use of Application-Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case the ASIP specialization involves a complex interaction between hardware- and software-related issues. In this paper we propose tools and methodologies to cope efficiently with this complexity from a multi-objective perspective. We present EPIC-Explorer, an open platform for estimation and system-level exploration of an EPIC/VLIW architecture. We first analyze the possible design objectives, showing that it is necessary, given the fundamental role played by the VLIW compiler in instruction scheduling, to evaluate the appropriateness of ILP-oriented compilation on a case-by-case basis. Then, in the architecture exploration phase, we will use a multi-objective genetic approach to obtain a set of Pareto-optimal configurations. Finally, by clustering the configurations thus obtained, we extract those representing possible trade-offs between the objectives, which are used as a starting point for evaluation via more accurate estimation models at a subsequent stage in the design flow.

In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.

Error correcting codes (ECCs) are commonly used as a protection against the soft errors. Single error correcting and double error detecting (SEC–DED) codes are generally used for this purpose. Such circuits are widely used in industry in all types of memory, including caches and embedded memory. In this paper, a new genetic design for ECC is proposed to perform SEC–DED in the memory check circuit. The design is aimed at finding the implementation of ECC which consumes minimal power. We formulate the ECC design into a permutable optimization problem and employ special genetic operators appropriate for this formulation. Experiments are performed to demonstrate the performance of the proposed method.

Power consumption of synchronous sequential circuits can be reduced by careful encoding of the states of the circuit. The idea is to reduce the average number of bit changes per state transition by finding an optimal state assignment. This state assignment problem is NP-hard, and existing techniques rely mainly on heuristic-based methods. The primary goal of this work is to assess the suitability of using complete advanced Boolean Satisfiability and Integer Linear Programming (ILP) methods in finding an optimized solution. We formulate the problem as a 0-1 ILP instance with power minimization being the objective. Using generic and commercial solvers, the proposed approach was tested on sample circuits from the MCNC benchmark suite. Furthermore, in an effort to accelerate the search process, circuits were checked for symmetries and symmetry breaking predicates were added whenever applicable. The experimental results provide a pragmatic insight into the problem and basis for further exploration.

In the process of image acquisition and transmission, data can be corrupted by impulse noise. This paper presented the removal of impulse noise in medical image by using Very Large Scale Integrated circuit (VLSI) implementation. The Low Cost Reduced Simple Edge Preserved De-noising (LCRSEPD) technique is introduced using Low Area Carry Select Adder (CSLA) to remove the salt and pepper noise instead of normal adder. Thus, LCRSEPD technique preserves visual performance and edge features in terms of quality and quantitative evaluation. By optimizing the architecture, low cost RSEPD can achieve low computational complexity that will reflect in area, power and delay. Compared to the previous VLSI implementations, the LCRSEPD implementation with CSLA adder has achieved good medical image quality and less hardware cost due to the reduction of area, power and delay.

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E$-$18J for 16-bit adder and 5.808E$-$18J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

In this paper, the Levy flight-based chicken swarm optimization (LFCSO) is proposed to follow the highest power of grid-joined photovoltaic (PV) framework. To analyze the grid-associated PV framework, the characteristics of current, power, voltage, and irradiance are determined. Because of the low yield voltage of the source PV, a big advance up converter with big productivity is required when the source PV is associated with the matrix power. A tale great advance up converter dependent on the exchanged capacitor and inductor is illustrated in this paper. The LFCSO algorithm with the adaptive neuro-fuzzy inference system is used to generate the control pulses of the transformer-coupled inductor DC–DC converter-less switched capacitor. While using the switched capacitor-coupled inductor, the voltage addition is expanded in the DC–DC converter and the power of PV is maximized. Here, the normal CSO algorithm is updated with the help of Levy flight functions to generate optimal results. To get the accurate optimal results, the output of the proposed LFCSO algorithm is given as the input of the ANFIS technique. After that, the optimal results are generated and they provide the pulses for the system. The working guideline is analyzed and the voltage addition is derived with the utilization of the proposed technique. From that point forward, it predicts the exact maximum power of the converter according to its inputs. Under the variety of solar irradiance and partial shading conditions (PSCs), the PV system is tested and its characteristics are analyzed in different time instants. The proposed LFCSO with ANFIS method is actualized in Simulink/MATLABstage, and the tracking executing is examined with a traditional method such as genetic algorithm (GA), perturb and observe (P&O) technique–neuro-fuzzy controller (NFC) and fuzzy logic controller (FLC) technique.

In this paper, a novel partial product generation (PPG) scheme has been proposed based on the shift and the add logic of multiplier bits to introduce a radix-4 and radix-16 signed binary multiplications (SBMs). The proposed PPG methodology encodes two bits for radix-4 and four bits for radix-16 at a time, whereas the traditional modified Booth encoding (MBE) for radix-4 and radix-16 encodes three bits and five bits, respectively, at a time, which offers the reduction of the encoder combinations. In the proposed design, the multiplication sign extension is pre-decided from the most significant bit (MSB) of the multiplier and the multiplicand, thereby subtraction operation for multiplication is removed from traditional MBE. The simulation results of the proposed SBMs architecture offer a significant improvement in power, delay and power-delay-product (PDP). The PDP was reduced by $\sim 79$%, $\sim 84$% and $\sim 85$%, respectively, with proposed radix-4 SBM and by $\sim 45$%, $\sim 64$% and $\sim 72$%, respectively, with proposed radix-16 SBM for $8\times 8\text{-},16\times 16$-, and $32\times 32$-bit multiplication, respectively, when compared with the existing state-of-the-art designs.

Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from $2\times 2$ to $45\times 45$ are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is $5000\times$ to $5500\times$ with respect to BookSim simulator.

Improved speed, reduced delay, reduced size and reduced power are the most important requirements of integrated circuits. The carry select adder (CSA) is one of the most important adders in most data processors for performing arithmetic operations. The speed of parallel adders can be enhanced CSA, which widens the area to speed and eliminates propagation delays. The major problem faced in CSA is inefficient area due to the usage of multiple pairs of Ripple carry adders (RCAs) for generating the sums and carry. This research paper proposes the modified 32-bit square root carry select adder (MSCSLA) to improve the direct digital synthesizer’s performance (DDS). DDS plays an effective role in the digital system due to its ability of broad frequency generation. Phase accumulator is the main component in the DDS synthesizer, where the speed of the adder is enhanced through MSCSLA. The general square root CSA still consumes more power due to the assembly of more RCAs. Hence, in the proposed approach, certain sets of RCAs are replaced with BEC1 (Binary to excess 1 convertor) to improve the speed and reduce the delay of the adder. Finally, the continuous sinusoidal waveform is attained by attenuating the high-frequency components by adopting a low pass filter. The entire structure of DDS is designed using Xilinx Verilog coding. The Simulation result shows better outcomes in terms of area, delay, power, and high performance in the DDS synthesizer compared to the existing CSAs. When compared to the existing adders, the area occupied by the proposed MSCSLA model is attained to be 636$\mu$m², the power is achieved as 50.125$\mu$W and delay is attained to be 1.280ns, which are comparatively less. When comparing delay and maximum frequency with the existing techniques, the proposed model obtained minimum delay and maximum frequency. The overall power consumption by the proposed model is also attained to be lower than the existing techniques.

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.

This paper presents how the space of spheres and shelling may be used to delete a point from a d-dimensional triangulation efficiently. In dimension two, if k is the degree of the deleted vertex, the complexity is O(k log k), but we notice that this number only applies to low cost operations, while time consuming computations are only done a linear number of times.

This algorithm may be viewed as a variation of Heller's algorithm,^1,2 which is popular in the geographic information system community. Unfortunately, Heller algorithm is false, as explained in this paper.