DELAY AND ENERGY EFFICIENT CODING TECHNIQUES FOR CAPACITIVE INTERCONNECTS
Abstract
In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.
