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In this paper, we review the potential applications of single-walled carbon nanotubes in three areas: passives (interconnects), actives (transistors), and antennas. In the area of actives, potential applications include transistors for RF and microwave amplifiers, mixers, detectors, and filters. We review the experimental state of the art, and present the theoretical predictions (where available) for ultimate device performance. In addition, we discuss fundamental parameters such as dc resistance as a function of length for individual, single-walled carbon nanotubes.

Carbon nanotubes (CNTs) as interconnects in integrated circuits (ICs) which are vertically aligned in growth with high tube density and long tube length are required. In this paper, we present a method to improve the height of CNTs. High-resolution transmission electron microscopic (TEM) images confirm CNTs top growth mode. By cutting and modifying the top of CNTs, the influences of different radii of apertures on interconnect resistance were studied. According to the analysis, we proposed a novel growth mechanism to improve growth height of CNTs interconnection structure and the top contact resistances of pre-cutting and post-cutting CNTs interconnection structure were forecasted. The result demonstrates that the electronic performances of the post-cutting CNTs interconnection structure with platinum (Pt)-protected layer are better than the ones of pre-cutting CNTs interconnection structure. The resistivity of the post-cutting CNTs interconnection structure with Pt-protected layer is $81.2\mathrm{\text{m}}\mathrm{\Omega }\cdot \mathrm{\text{cm}}$, which is much less than that of post-cutting CNTs interconnect structure $508.8\mathrm{\text{m}}\mathrm{\Omega }\cdot \mathrm{\text{cm}}$. In what follows, the resistance of the contacted area of pre-cutting CNTs interconnection structure is 31 $\mathrm{\Omega }$, which is much less than that of post-cutting CNTs interconnection structure 439 $\mathrm{\Omega }$. This constitutes a significant step to realize longer CNTs interconnects with complementary metal oxide semiconductor (CMOS) contact modules.

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be one useful figure of merit. It is shown that as the effective damping factor of a signal increases, an RC model is sufficiently accurate to characterize the waveform. The rise time of the input signal driving an RLC tree is shown to be a second factor that affects the relative significance of inductance. As the rise time of the input signal increases as compared to the effective LC time constant at a specific node within an RLC tree, the signal at this node will no longer exhibit the effects of inductance. It is demonstrated that a single line analysis to determine the importance of including inductance to characterize an interconnect line that is a part of a tree is invalid in many cases and can lead to erroneous conclusions. The error exhibited by single line analysis is due to the large interaction among the branches of the tree.

The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

This paper presents an efficient and accurate approach to calculate effective capacitances in the presence of RC interconnect loads. In the precharacterization process, the gate model is selected such that the output of the model matches both the delay and the shape of the real gate response. To determine the effective capacitance, a novel algorithm is developed to efficiently and accurately calculate the propagation delay from circuit elements. This algorithm requires at most two iterations to obtain effective capacitances that produce gate delays within 4% of HSPICE results. This is at most half the time required by the currently used method to calculate effective capacitances.

In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.

In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and overshoot/undershoot analyses for the application of signal interconnects. The results are compared with that of the traditional Cu-based interconnects. The results show that GNR is better than Cu as far as IR drop, SSN, gate oxide reliability and hot carrier reliability are concerned. Our investigation reveals that GNR can be better than the Cu interconnects from all aspects with a multilayer GNR structure. The present graphene-based interconnect technology needs to be advanced, so that the metal–graphene contact resistance is minimized and multilayer GNR structure with large number of graphene layers is supported.

On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

In recent years, model order reduction (MOR) of interconnect system has become an important technique to reduce the computation complexity and improve the verification efficiency in the nanometer VLSI design. The Krylov subspaces techniques in existing MOR methods are efficient, and have become the methods of choice for generating small-scale macro-models of the large-scale multi-port RCL networks that arise in VLSI interconnect analysis. Although the Krylov subspace projection-based MOR methods have been widely studied over the past decade in the electrical computer-aided design community, all of them do not provide a best optimal solution in a given order. In this paper, a minimum norm least-squares solution for MOR by Krylov subspace methods is proposed. The method is based on generalized inverse (or pseudo-inverse) theory. This enables a new criterion for MOR-based Krylov subspace projection methods. Two numerical examples are used to test the PRIMA method based on the method proposed in this paper as a standard model.

In this work, we have presented the temperature-dependent analytical time domain model for top-contact multilayer graphene nanoribbon (TC-MLGNR) and side-contact multilayer graphene nanoribbon (SC-MLGNR) interconnects for 16nm technology node. Using this analytical model, the effective mean free path (MFP) is calculated for different temperatures and then the resistance of GNR interconnect is calculated. The lower resistance of MLGNR is one of the important factors to reduce interconnect delay. The equivalent capacitance for TC-MLGNR is also calculated. It is observed that the performance of graphene interconnects seriously deteriorates due to the presence of the interlayer capacitance. The presence of this interlayer capacitance increases the equivalent capacitance which is the dominant factor that inhibits the performance of TC-MLGNR interconnects. Further, the delay ratio between copper and TC-MLGNR for different interconnect lengths and for three different temperatures (233K, 300K, 378K) is calculated. It is observed that for longer interconnect lengths, the improvement in delay in TC-MLGNR is less as compared to traditional copper-based interconnect at low temperature. Further, power delay product (PDP) of copper and TC-MLGNR for different interconnect lengths and for three different temperatures is also calculated. It is shown that TC-MLGNR interconnects have better PDP than copper interconnects. The crosstalk analysis is performed to estimate the noise and overshoot/undershoot in TC-MLGNR and SC-MLGNR interconnects. It is shown that SC-MLGNR interconnect has better performance as far as the crosstalk is concerned as compared to that of Cu and TC-MLGNR interconnects.

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

Multichip modules (MCMs) are an advanced packaging technique that features greater packing density and performance than traditional packaging technologies. At present, the lack of a merchant MCM infrastructure and high costs are together limiting the widespread use of MCM technologies outside the captive markets. However, in the near future, current packaging technologies will not be able to deliver the equivalent size, weight and reliability advantages offered by MCM technology. Evidence shows that MCMs are migrating towards low- and mid-range computer applications thanks to technological advancements and to the increased demands for higher performance within this market. This paper presents MCM classifications, design issues, interconnection techniques, trends in the technology and the changing marketplace and applications for these packaging systems.

This paper introduces an accurate analysis of time domain response of carbon nanotube (CNT) interconnects based on distributed RLC model that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous principle calculations, accurate expressions for the transfer function of these lines and their time domain response have been presented. It has been shown that the second-order transfer function cannot represent the distributed behavior of the long CNT interconnects, and the fourth-order approximation offers a better result. Also, the time response of a driven long CNT interconnect versus length and diameter have been studied. The obtained results show that the overshoot increases and the time delay decreases with increasing the CNT diameter, such that with the diameter value of 10 nm for a 3.3 mm CNT interconnect, the maximum overshoot value reaches about 95% of the amplitude of the driver input. On the contrary, the overshoot increases and the time delay decreases with decreasing the length of the CNT, such that with the length value of 1 mm for a 5 nm diameter CNT interconnect, the maximum overshoot reaches about 90% of the amplitude of the driver input.

This chapter presents gold passivated NiW Compressible MicroInterconnects (CMIs) with 75 μm height and 150 μm in-line pitch. The CMIs are batch fabricated using CMOS compatible processes. The fabricated CMIs have a measured compliance of up to 13.12 mm/N and demonstrate 45 μm elastic vertical range of motion. Moreover, the CMIs are shown to return to their original geometrical profile after several deflections and consequently are able to maintain contact with their corresponding pads at all times. The measured four-point resistance of the CMI, which includes contact resistance, is as low as 176.3mΩ.

In this paper, we review the potential applications of single-walled carbon nanotubes in three areas: passives (interconnects), actives (transistors), and antennas. In the area of actives, potential applications include transistors for RF and microwave amplifiers, mixers, detectors, and filters. We review the experimental state of the art, and present the theoretical predictions (where available) for ultimate device performance. In addition, we discuss fundamental parameters such as dc resistance as a function of length for individual, single-walled carbon nanotubes.