Journal of Circuits, Systems and Computers

Advances in magnetoresistive type sensors provide a new technique for nondestructive evaluation of metal structures. Giant magnetoresistive and giant magnetoimpedance sensors provide high sensitivity and reduced size with GMI sensors also adding capabilities of high frequency range of measurements. Being produced with thin film processing techniques, the manufacturing cost of these sensors is low. An example is considered of detecting defects in printed circuit boards. System details and experimental results are provided. Computational modeling validation is introduced based on finite element as well as method of moments analysis.

In this paper, we propose to integrate an embedding of Property Specification Language (PSL) in Abstract State Machines Language (AsmL) with a top–down design for verification approach in order to enable the model checking of large systems at the early stages of the design process. We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL properties as a part of the design. For verification, we propose a technique based on the AsmL tool that translates the code containing both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage of the AsmL language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both C# code and FSMs from AsmL models. We applied our approach on the PCI-X bus standard, which AsmL model was constructed from the informal standard specifications and a subsequent UML model. Experimental results on the PCI-X bus case study showed a superiority of our approach to conventional verification.

Security of cryptographic circuits is a major concern. Smartcards are targeted by sophisticated attacks like fault attacks that combine physical disturbance and cryptanalysis. We propose a methodology and a tool (PAFI) to analyze the robustness of circuits under fault attacks using fault injection in simulation. The number of injections is reduced by taking into account the function of the latches in the whole circuit. We tested a circuit implementing the cryptosystem AES and showed that our approach reduces the number of fault injections to be performed (- 80%). Moreover, most of the selected injection points are the ones that lead to known fault attacks (95%).

This paper presents a novel approach for the generation of periodic waveforms in digital form using Field Programmable Gate Array (FPGA) and orthogonal functions. The orthogonal function consists of a set of Rademacher–Walsh Functions, and utilizing these functions, virtually any periodic waveform can be synthesized. Recent technological advancements in FPGA and availability of sophisticated digital design tools have made it possible to realize high-speed waveform generator in a cost-effective way. We demonstrate the proposed technique for the successful generation of Trapezoidal, Sinusoidal, Triangular waveforms, and a complex version of these waveforms. Simulation results for the various waveforms implemented in Xilinx Spartan-3 (XC3S200-4FT256) FPGA are presented both in analog and digital forms, and validated in MATLAB. The designed circuit can be easily integrated as a module for System-on-Chip (SoC) for on-chip waveform generation

Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems.

In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.

An original method for generating components that capture the occurrence of events is proposed, and logical and temporal properties of hardware/software embedded systems are monitored. The properties are written in PSL, under the form of assertions in declarative form. The method includes the construction of a library of primitive digital components for the PSL temporal and sequence operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny.

We propose a new flow for hardware/software co-design, based on the platform-based design, which forms a base for further automation attempts of the co-design process. We prove the applicability of the proposed flow on co-designing generic systems as well as RTOS-based systems. Our proposed flow starts with a software-only solution in which all system functionality is described as embedded software targeting a selected platform. Then, the flow iterates through co-verification, profiling, partitioning, and co-synthesis until the design criteria are met. We present four test cases to show the effectiveness of our proposed methodology. The main contribution added by the proposed methodology is incorporating the target application platform at the first stage of the flow then applying our iterative co-design algorithm without altering the main platform. This opposes other co-design methodologies that let the platform details be synthesized at later stages, widening the exploration space to be unrealistic and producing platforms that may vary to a large extent compared to the pre-verified application platform. The other contribution is the study provided on the effect of co-design on the behavior of RTOS-based platforms, which brings the flow closer to real-case problems, where most embedded systems utilize RTOS in their software stack.

Queue modeling is an important step in Networks-on-Chip (NoC) design to understand and estimate the system behavior at early design phases. Choosing queue parameters, such as queue size, maximum packet arrival rate, packet service rate, directly impacts the performance and silicon area of the overall NoC-based design. In this paper, we propose a new 2D M/D/1/B queuing model for NoC routers. Using our model, we prove that packet service rate impacts throughput significantly. On the other hand, changing the queue size, within acceptable ranges for NoC applications, does not have a noticeable effect on the throughput. Through a case study implementation on FPGA, we explain how this model could be used in different applications to obtain design parameters at higher levels of abstraction. Synthesis and performance analysis are performed to validate the proposed model.

Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placement of these tasks result in area fragmentation leading to poor utilization of chip resources.

In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at runtime. Next, we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well-known bottom left, first fit, and best-fit placement strategies. In real-time environment, we achieve an improvement in miss ratio when using the fragmentation-aware placement over the bottom left placement strategy.

Current multimedia design processes suffer from the excessively large time spent on testing new IP-blocks with references based on large video encoders specifications (usually several thousands lines of code). The appropriate testing of a single IP-block may require the conversion of the overall encoder from software to hardware, which is difficult to complete in the short time required by the competition-driven reduced time-to-market demanded for the adoption of a new video coding standard. This paper presents a new design flow to accelerate the conformance testing of an IP-block using the H.264/AVC software reference model. An example block of the simplified 8 × 8 transformation and quantization, which is adopted in FRExt, is provided as a case study demonstrating the effectiveness of the approach.

This paper concerns the design method and implementation of main modules, dedicated to miniaturized digital ultrasonic devices, using advanced System-on-Chip technique. It is intended to diagnostic imaging applications such as echography. The proposed implementation allows the integration of all acquisition front end as well as signal and video processing on only one single chip. It will make possible to visualize the ultrasound images in real time. It requires high resolution and real-time image processing. The proposed design, which integrates the B-mode processing modules, includes digital beamforming, quadrature demodulation of RF signals, digital filtering, envelope detection, and video processing of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a 90° angle of view span. The design uses a minimum size look-up memory to store the initial scan information. Rapid prototyping based on ARM/FPGA platform combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.