Journal of Circuits, Systems and Computers

Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely, Miller and cascode compensations are compared from power efficiency point of view. To accomplish this, cascode-compensated topologies are basically analyzed to derive the required equations for the comparison. In the analysis, a new method to take into account the effect of transfer function zeros is proposed. By assuming that the zeros' magnitudes are fairly nondominant, the method increases the accuracy of the analyses. The relationships show that for the same specifications, cascode compensation is more power-efficient than Miller compensation, especially for heavy capacitive loads. This has been confirmed by SPICE simulations.

Multiple project wafers (MPWs) containing different chip designs from many customers serves as an important vehicle for gaining access to advanced semiconductor process technology for prototyping innovative designs or low-volume production. In this paper, a comprehensive study on the methods for determining dicing plans for MPW was carried out. Dicing plans can be used to determine the number of MPWs needed to be fabricated before chip fabrication and employed to saw the wafers after fabrication. Several methods based on integer linear programming formulation and a heuristic based on simulated annealing was proposed. Through conducting experiments with industrial test cases, these proposed methods can achieve up to 50% wafer reduction in some cases and on average 18% and 38% reduction for low- and high-volume production, respectively. This study makes a contribution to MPW dicing and is also instrumental in developing better reticle floorplanning methods.

The history of Tow–Thomas second-order filter is reviewed. Two alternative generation methods of the Tow–Thomas filter are discussed. The first is a generation method from the second-order passive RLC filter and the second is from the multiple feedbacks inverting low-pass filter using a single op amp. Several forms of the circuit are briefly reviewed. Passive and active compensation methods to improve the circuit performance for high-Q designs are summarized. Spice simulation results are included.

Traditional continuous-time filters are of integer order. However, using fractional calculus, filters may also be represented by the more general fractional-order differential equations in which case integer-order filters are only a tight subset of fractional-order filters. In this work, we show that low-pass, high-pass, band-pass, and all-pass filters can be realized with circuits incorporating a single fractance device. We derive expressions for the pole frequencies, the quality factor, the right-phase frequencies, and the half-power frequencies. Examples of fractional passive filters supported by numerical and PSpice simulations are given.

Designing wide-band amplifiers has become one of the important issues in wireless and optical high-performance System-on-Chip applications. In this paper, we present a newly developed analytical tapering factor that determines the optimal size of each stage of the cascaded amplifier. The utilization of our developed tapering factor can lead to a significant improvement in the amplifier bandwidth as compared with the standard cascaded amplifier unity tapering factor.

Parasitic inductance of global interconnects has gained much attention in the recent past since the inductance can no longer be neglected due to different design and fabrication issues. This has led to a paradigm shift from RC to RLC modeling of global interconnects in modern integrated circuits. However, the extraction of inductance is often expensive and presents a bottleneck in performing RLC analysis of interconnects. Unlike capacitance, the frequency dependence of current distribution through return paths present a major challenge in inductance extraction. In this paper, an efficient analytical model of frequency dependent self-inductance that can be applied to model a wide range of real design scenarios was presented. The model is based on the determination of the inductances at low and very high frequencies, an intermediate frequency point and the corresponding slope of the inductance frequency response. It is demonstrate that the approach is computationally efficient and it produces accurate values of frequency dependent inductance. It is also investigate how the frequency dependence of loop self-inductance affects the RLC delay and show that the pessimism in RLC propagation delay estimation could be as high as 49% if the frequency dependence of inductance is not considered properly. Thus, realistic (less pessimistic) delay values can be obtained using our model, leading to improved system performance.

To reduce the intermediate storage capacitor voltage stress in single-stage power-factor-corrected (S²PFC) converters due to the change of load, some effective approaches such as variable frequency control and negative bus voltage feedback have been proposed. However, this intermediate capacitor voltage still varies largely against the change of line voltage. This paper proposes a S²PFC converter which is constructed in a way such that the amount of energy to and from the intermediate storage capacitor can be varied when the line voltage is changed, hence narrowed the range of intermediate capacitor voltage fluctuation. This is achieved by an auxiliary bidirectional switch, which operates at zero-voltage-switching (ZVS) condition. A dual-loop voltage mode control is proposed for the converter to achieve power factor correction, output voltage regulation, and intermediate capacitor voltage control simultaneously. Simulation and experimental results show that the proposed approach is effective.

In this paper, an algorithm for data embedding in images is proposed. The algorithm is based on using the Discrete Wavelet Transform domain to embed digital data into images. In order to increase the algorithm robustness and ensure the authentication of the data extracted, error detection/correction coding techniques are used to encode the embedded data. The proposed algorithm is blind, i.e., the embedded data are extracted and authenticated without any reference to the original image or data. Experimental results demonstrate the low perceptibility of distortions caused by the data embedding and the high algorithm robustness against several common image-processing operations.

The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed.

The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at the same time to vie for a share of the burgeoning industry, higher educational institutions and universities from all around the globe are placing greater than ever emphasis on IC design research. Most importantly, strenuous efforts in a holistic manner are being made by each university in order to elicit outstanding and top-notch research in IC design. The authors have conducted a detailed and extensive survey to rank the various universities of the world in the field of IC design based on their research performance. In fact, assessments in the form of ranking have gained prominence over the recent years captivating the attention of a large number of students and universities. It helps the students in knowing how each university is progressing in a particular field and in turn helps the universities in analyzing their positions globally to remain competitive. Three ranking indicators, namely the Number of Publications, Citation Counts, and Cites per Paper have been chosen. The methodology used in ranking is also reported. The universities occupying the top echelons in IC design research are identified and a proven three-pronged approach for eliciting outstanding research performance is discussed.